4 * Clocks for TI814X based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
18 #define PRCM_MOD_EN 0x2
24 #define L3_OSC_SRC OSC_SRC0
28 #define DCO_HS2_MIN 500
29 #define DCO_HS2_MAX 1000
30 #define DCO_HS1_MIN 1000
31 #define DCO_HS1_MAX 2000
33 #define SELFREQDCO_HS2 0x00000801
34 #define SELFREQDCO_HS1 0x00001001
39 #define MPU_CLKCTRL 0x1
44 #define L3_CLKCTRL 0x801
49 #define DDR_CLKCTRL 0x801
51 /* ADPLLJ register values */
52 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
53 #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
54 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
55 #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
56 #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
57 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
58 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
59 #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
60 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
61 #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
62 #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
63 #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
64 ADPLLJ_CLKCTRL_CLKOUTEN | \
65 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
66 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
68 #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
69 #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
70 #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
71 ADPLLJ_STATUS_FREQLOCK)
72 #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
73 #define ADPLLJ_STATUS_BYPASS (1 << 0)
74 #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
77 #define ADPLLJ_TENABLE_ENB (1 << 0)
78 #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
80 #define ADPLLJ_M2NDIV_M2SHIFT 16
82 #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
83 #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
84 #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
90 unsigned int tenablediv;
95 unsigned int fracctrl;
98 unsigned int rampctrl;
101 #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
104 #define ENET_CLKCTRL_CMPL 0x30000
106 #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
109 unsigned int resv0[2];
110 unsigned int l3fastclkstctrl;
111 unsigned int resv1[1];
112 unsigned int pciclkstctrl;
113 unsigned int resv2[1];
114 unsigned int ducaticlkstctrl;
115 unsigned int resv3[1];
116 unsigned int emif0clkctrl;
117 unsigned int emif1clkctrl;
118 unsigned int dmmclkctrl;
119 unsigned int fwclkctrl;
120 unsigned int resv4[10];
121 unsigned int usbclkctrl;
122 unsigned int resv5[1];
123 unsigned int sataclkctrl;
124 unsigned int resv6[4];
125 unsigned int ducaticlkctrl;
126 unsigned int pciclkctrl;
129 #define CM_ALWON_BASE (PRCM_BASE + 0x1400)
132 unsigned int l3slowclkstctrl;
133 unsigned int ethclkstctrl;
134 unsigned int l3medclkstctrl;
135 unsigned int mmu_clkstctrl;
136 unsigned int mmucfg_clkstctrl;
137 unsigned int ocmc0clkstctrl;
138 unsigned int vcpclkstctrl;
139 unsigned int mpuclkstctrl;
140 unsigned int sysclk4clkstctrl;
141 unsigned int sysclk5clkstctrl;
142 unsigned int sysclk6clkstctrl;
143 unsigned int rtcclkstctrl;
144 unsigned int l3fastclkstctrl;
145 unsigned int resv0[67];
146 unsigned int mcasp0clkctrl;
147 unsigned int mcasp1clkctrl;
148 unsigned int mcasp2clkctrl;
149 unsigned int mcbspclkctrl;
150 unsigned int uart0clkctrl;
151 unsigned int uart1clkctrl;
152 unsigned int uart2clkctrl;
153 unsigned int gpio0clkctrl;
154 unsigned int gpio1clkctrl;
155 unsigned int i2c0clkctrl;
156 unsigned int i2c1clkctrl;
157 unsigned int mcasp345clkctrl;
158 unsigned int atlclkctrl;
159 unsigned int mlbclkctrl;
160 unsigned int pataclkctrl;
161 unsigned int resv1[1];
162 unsigned int uart3clkctrl;
163 unsigned int uart4clkctrl;
164 unsigned int uart5clkctrl;
165 unsigned int wdtimerclkctrl;
166 unsigned int spiclkctrl;
167 unsigned int mailboxclkctrl;
168 unsigned int spinboxclkctrl;
169 unsigned int mmudataclkctrl;
170 unsigned int resv2[2];
171 unsigned int mmucfgclkctrl;
172 unsigned int resv3[2];
173 unsigned int ocmc0clkctrl;
174 unsigned int vcpclkctrl;
175 unsigned int resv4[2];
176 unsigned int controlclkctrl;
177 unsigned int resv5[2];
178 unsigned int gpmcclkctrl;
179 unsigned int ethernet0clkctrl;
180 unsigned int ethernet1clkctrl;
181 unsigned int mpuclkctrl;
182 unsigned int debugssclkctrl;
183 unsigned int l3clkctrl;
184 unsigned int l4hsclkctrl;
185 unsigned int l4lsclkctrl;
186 unsigned int rtcclkctrl;
187 unsigned int tpccclkctrl;
188 unsigned int tptc0clkctrl;
189 unsigned int tptc1clkctrl;
190 unsigned int tptc2clkctrl;
191 unsigned int tptc3clkctrl;
192 unsigned int resv7[4];
193 unsigned int dcan01clkctrl;
194 unsigned int mmchs0clkctrl;
195 unsigned int mmchs1clkctrl;
196 unsigned int mmchs2clkctrl;
197 unsigned int custefuseclkctrl;
200 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
203 unsigned int pllcfg0;
204 unsigned int pllcfg1;
205 unsigned int pllcfg2;
206 unsigned int pllcfg3;
207 unsigned int pllcfg4;
208 unsigned int pllstatus;
209 unsigned int rxstatus;
210 unsigned int txstatus;
211 unsigned int testcfg;
214 #define SEL_IN_FREQ (0x1 << 31)
215 #define DIGCLRZ (0x1 << 30)
216 #define ENDIGLDO (0x1 << 4)
217 #define APLL_CP_CURR (0x1 << 3)
218 #define ENBGSC_REF (0x1 << 2)
219 #define ENPLLLDO (0x1 << 1)
220 #define ENPLL (0x1 << 0)
222 #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
223 #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
224 #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
225 #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
228 #define PLL_LOCK (0x1 << 0)
230 #define ENSATAMODE (0x1 << 31)
231 #define PLLREFSEL (0x1 << 30)
232 #define MDIVINT (0x4b << 18)
233 #define EN_CLKAUX (0x1 << 5)
234 #define EN_CLK125M (0x1 << 4)
235 #define EN_CLK100M (0x1 << 3)
236 #define EN_CLK50M (0x1 << 2)
238 #define SATA_PLLCFG1 (ENSATAMODE | \
246 #define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
247 #define PLLDO_EN_LDO_STABLE (0x1 << 11)
248 #define PLLDO_EN_BUF_CUR (0x1 << 7)
249 #define PLLDO_EN_LP (0x1 << 6)
250 #define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
252 #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
253 PLLDO_EN_LDO_STABLE | \
256 PLLDO_CTRL_TRIM_1_4V)
258 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
259 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
260 const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
263 * Enable the peripheral clock for required peripherals
265 static void enable_per_clocks(void)
268 writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
269 while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
273 writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
274 writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
275 while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
277 writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
278 while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
283 * select the HS1 or HS2 for DCO Freq
286 static u32 pll_dco_freq_sel(u32 clkout_dco)
288 if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
289 return SELFREQDCO_HS2;
290 else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
291 return SELFREQDCO_HS1;
297 * select the sigma delta config
298 * return: sigma delta val
300 static u32 pll_sigma_delta_val(u32 clkout_dco)
305 frac_div = (float) clkout_dco / 250;
306 frac_div = frac_div + 0.90;
307 sig_val = (int)frac_div;
308 sig_val = sig_val << 24;
314 * configure individual ADPLLJ
316 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
317 u32 clkctrl_val, int adpllj)
319 const struct ad_pll *adpll = (struct ad_pll *)base;
320 u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
321 u32 sig_val = 0, hs_mod = 0;
323 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
326 /* calculate clkout_dco */
327 clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
329 /* sigma delta & Hs mode selection skip for ADPLLS*/
331 sig_val = pll_sigma_delta_val(clkout_dco);
332 hs_mod = pll_dco_freq_sel(clkout_dco);
336 read_clkctrl = readl(&adpll->clkctrl);
337 writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
338 while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
339 != ADPLLJ_STATUS_BYPASSANDACK)
343 read_clkctrl = readl(&adpll->clkctrl);
344 writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
347 * ref_clk = 20/(n + 1);
348 * clkout_dco = ref_clk * m;
349 * clk_out = clkout_dco/m2;
351 read_clkctrl = readl(&adpll->clkctrl) &
352 ~(ADPLLJ_CLKCTRL_LPMODE |
353 ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
354 ADPLLJ_CLKCTRL_REGM4XEN);
355 writel(m2nval, &adpll->m2ndiv);
356 writel(mn2val, &adpll->mn2div);
358 /* Skip for modena(ADPLLS) */
360 writel(sig_val, &adpll->fracdiv);
361 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
364 /* Load M2, N2 dividers of ADPLL */
365 writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
366 writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
368 /* Load M, N dividers of ADPLL */
369 writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
370 writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
372 /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
373 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
375 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
378 /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
379 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
380 writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
382 /* Wait for phase and freq lock */
383 while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
384 ADPLLJ_STATUS_PHSFRQLOCK)
388 static void unlock_pll_control_mmr(void)
390 /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
391 writel(0x1EDA4C3D, 0x481C5040);
392 writel(0x2FF1AC2B, 0x48140060);
393 writel(0xF757FDC0, 0x48140064);
394 writel(0xE2BC3A6D, 0x48140068);
395 writel(0x1EBF131D, 0x4814006c);
396 writel(0x6F361E05, 0x48140070);
399 static void mpu_pll_config(void)
401 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
404 static void l3_pll_config(void)
406 u32 l3_osc_src, rd_osc_src = 0;
408 l3_osc_src = L3_OSC_SRC;
409 rd_osc_src = readl(OSC_SRC_CTRL);
411 if (OSC_SRC0 == l3_osc_src)
412 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
414 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
416 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
419 void ddr_pll_config(unsigned int ddrpll_m)
421 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
424 void sata_pll_config(void)
427 * This sequence for configuring the SATA PLL
428 * resident in the control module is documented
429 * in TI8148 TRM section 21.3.1
431 writel(SATA_PLLCFG1, &spll->pllcfg1);
434 writel(SATA_PLLCFG3, &spll->pllcfg3);
437 writel(SATA_PLLCFG0_1, &spll->pllcfg0);
440 writel(SATA_PLLCFG0_2, &spll->pllcfg0);
443 writel(SATA_PLLCFG0_3, &spll->pllcfg0);
446 writel(SATA_PLLCFG0_4, &spll->pllcfg0);
449 while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
453 void enable_dmm_clocks(void)
455 writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
456 writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
457 writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
458 while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
460 writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
461 while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
463 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
465 writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
466 while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
468 writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
469 while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
473 void setup_clocks_for_console(void)
475 unlock_pll_control_mmr();
477 writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
478 while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
482 * Configure the PLL/PRCM for necessary peripherals
486 /* Enable the control module */
487 writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
494 /* Enable the required peripherals */