4 * Clocks for TI814X based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
26 #define PRCM_MOD_EN 0x2
32 #define L3_OSC_SRC OSC_SRC0
36 #define DCO_HS2_MIN 500
37 #define DCO_HS2_MAX 1000
38 #define DCO_HS1_MIN 1000
39 #define DCO_HS1_MAX 2000
41 #define SELFREQDCO_HS2 0x00000801
42 #define SELFREQDCO_HS1 0x00001001
47 #define MPU_CLKCTRL 0x1
52 #define L3_CLKCTRL 0x801
57 #define DDR_CLKCTRL 0x801
59 /* ADPLLJ register values */
60 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
61 #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
62 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
63 #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
64 #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
65 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
66 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
67 #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
68 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
69 #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
70 #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
71 #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
72 ADPLLJ_CLKCTRL_CLKOUTEN | \
73 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
74 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
76 #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
77 #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
78 #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
79 ADPLLJ_STATUS_FREQLOCK)
80 #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
81 #define ADPLLJ_STATUS_BYPASS (1 << 0)
82 #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
85 #define ADPLLJ_TENABLE_ENB (1 << 0)
86 #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
88 #define ADPLLJ_M2NDIV_M2SHIFT 16
90 #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
91 #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
92 #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
98 unsigned int tenablediv;
101 unsigned int fracdiv;
103 unsigned int fracctrl;
106 unsigned int rampctrl;
109 #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
112 #define ENET_CLKCTRL_CMPL 0x30000
114 #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
117 unsigned int resv0[2];
118 unsigned int l3fastclkstctrl;
119 unsigned int resv1[1];
120 unsigned int pciclkstctrl;
121 unsigned int resv2[1];
122 unsigned int ducaticlkstctrl;
123 unsigned int resv3[1];
124 unsigned int emif0clkctrl;
125 unsigned int emif1clkctrl;
126 unsigned int dmmclkctrl;
127 unsigned int fwclkctrl;
128 unsigned int resv4[10];
129 unsigned int usbclkctrl;
130 unsigned int resv5[1];
131 unsigned int sataclkctrl;
132 unsigned int resv6[4];
133 unsigned int ducaticlkctrl;
134 unsigned int pciclkctrl;
137 #define CM_ALWON_BASE (PRCM_BASE + 0x1400)
140 unsigned int l3slowclkstctrl;
141 unsigned int ethclkstctrl;
142 unsigned int l3medclkstctrl;
143 unsigned int mmu_clkstctrl;
144 unsigned int mmucfg_clkstctrl;
145 unsigned int ocmc0clkstctrl;
146 unsigned int vcpclkstctrl;
147 unsigned int mpuclkstctrl;
148 unsigned int sysclk4clkstctrl;
149 unsigned int sysclk5clkstctrl;
150 unsigned int sysclk6clkstctrl;
151 unsigned int rtcclkstctrl;
152 unsigned int l3fastclkstctrl;
153 unsigned int resv0[67];
154 unsigned int mcasp0clkctrl;
155 unsigned int mcasp1clkctrl;
156 unsigned int mcasp2clkctrl;
157 unsigned int mcbspclkctrl;
158 unsigned int uart0clkctrl;
159 unsigned int uart1clkctrl;
160 unsigned int uart2clkctrl;
161 unsigned int gpio0clkctrl;
162 unsigned int gpio1clkctrl;
163 unsigned int i2c0clkctrl;
164 unsigned int i2c1clkctrl;
165 unsigned int mcasp345clkctrl;
166 unsigned int atlclkctrl;
167 unsigned int mlbclkctrl;
168 unsigned int pataclkctrl;
169 unsigned int resv1[1];
170 unsigned int uart3clkctrl;
171 unsigned int uart4clkctrl;
172 unsigned int uart5clkctrl;
173 unsigned int wdtimerclkctrl;
174 unsigned int spiclkctrl;
175 unsigned int mailboxclkctrl;
176 unsigned int spinboxclkctrl;
177 unsigned int mmudataclkctrl;
178 unsigned int resv2[2];
179 unsigned int mmucfgclkctrl;
180 unsigned int resv3[2];
181 unsigned int ocmc0clkctrl;
182 unsigned int vcpclkctrl;
183 unsigned int resv4[2];
184 unsigned int controlclkctrl;
185 unsigned int resv5[2];
186 unsigned int gpmcclkctrl;
187 unsigned int ethernet0clkctrl;
188 unsigned int ethernet1clkctrl;
189 unsigned int mpuclkctrl;
190 unsigned int debugssclkctrl;
191 unsigned int l3clkctrl;
192 unsigned int l4hsclkctrl;
193 unsigned int l4lsclkctrl;
194 unsigned int rtcclkctrl;
195 unsigned int tpccclkctrl;
196 unsigned int tptc0clkctrl;
197 unsigned int tptc1clkctrl;
198 unsigned int tptc2clkctrl;
199 unsigned int tptc3clkctrl;
200 unsigned int resv7[4];
201 unsigned int dcan01clkctrl;
202 unsigned int mmchs0clkctrl;
203 unsigned int mmchs1clkctrl;
204 unsigned int mmchs2clkctrl;
205 unsigned int custefuseclkctrl;
208 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
211 unsigned int pllcfg0;
212 unsigned int pllcfg1;
213 unsigned int pllcfg2;
214 unsigned int pllcfg3;
215 unsigned int pllcfg4;
216 unsigned int pllstatus;
217 unsigned int rxstatus;
218 unsigned int txstatus;
219 unsigned int testcfg;
222 #define SEL_IN_FREQ (0x1 << 31)
223 #define DIGCLRZ (0x1 << 30)
224 #define ENDIGLDO (0x1 << 4)
225 #define APLL_CP_CURR (0x1 << 3)
226 #define ENBGSC_REF (0x1 << 2)
227 #define ENPLLLDO (0x1 << 1)
228 #define ENPLL (0x1 << 0)
230 #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
231 #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
232 #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
233 #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
236 #define PLL_LOCK (0x1 << 0)
238 #define ENSATAMODE (0x1 << 31)
239 #define PLLREFSEL (0x1 << 30)
240 #define MDIVINT (0x4b << 18)
241 #define EN_CLKAUX (0x1 << 5)
242 #define EN_CLK125M (0x1 << 4)
243 #define EN_CLK100M (0x1 << 3)
244 #define EN_CLK50M (0x1 << 2)
246 #define SATA_PLLCFG1 (ENSATAMODE | \
254 #define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
255 #define PLLDO_EN_LDO_STABLE (0x1 << 11)
256 #define PLLDO_EN_BUF_CUR (0x1 << 7)
257 #define PLLDO_EN_LP (0x1 << 6)
258 #define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
260 #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
261 PLLDO_EN_LDO_STABLE | \
264 PLLDO_CTRL_TRIM_1_4V)
266 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
267 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
268 const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
271 * Enable the peripheral clock for required peripherals
273 static void enable_per_clocks(void)
276 writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
277 while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
281 writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
282 while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
286 writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
287 writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
288 while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
290 writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
291 while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
296 * select the HS1 or HS2 for DCO Freq
299 static u32 pll_dco_freq_sel(u32 clkout_dco)
301 if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
302 return SELFREQDCO_HS2;
303 else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
304 return SELFREQDCO_HS1;
310 * select the sigma delta config
311 * return: sigma delta val
313 static u32 pll_sigma_delta_val(u32 clkout_dco)
318 frac_div = (float) clkout_dco / 250;
319 frac_div = frac_div + 0.90;
320 sig_val = (int)frac_div;
321 sig_val = sig_val << 24;
327 * configure individual ADPLLJ
329 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
330 u32 clkctrl_val, int adpllj)
332 const struct ad_pll *adpll = (struct ad_pll *)base;
333 u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
334 u32 sig_val = 0, hs_mod = 0;
336 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
339 /* calculate clkout_dco */
340 clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
342 /* sigma delta & Hs mode selection skip for ADPLLS*/
344 sig_val = pll_sigma_delta_val(clkout_dco);
345 hs_mod = pll_dco_freq_sel(clkout_dco);
349 read_clkctrl = readl(&adpll->clkctrl);
350 writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
351 while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
352 != ADPLLJ_STATUS_BYPASSANDACK)
356 read_clkctrl = readl(&adpll->clkctrl);
357 writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
360 * ref_clk = 20/(n + 1);
361 * clkout_dco = ref_clk * m;
362 * clk_out = clkout_dco/m2;
364 read_clkctrl = readl(&adpll->clkctrl) &
365 ~(ADPLLJ_CLKCTRL_LPMODE |
366 ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
367 ADPLLJ_CLKCTRL_REGM4XEN);
368 writel(m2nval, &adpll->m2ndiv);
369 writel(mn2val, &adpll->mn2div);
371 /* Skip for modena(ADPLLS) */
373 writel(sig_val, &adpll->fracdiv);
374 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
377 /* Load M2, N2 dividers of ADPLL */
378 writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
379 writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
381 /* Load M, N dividers of ADPLL */
382 writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
383 writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
385 /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
386 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
388 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
391 /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
392 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
393 writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
395 /* Wait for phase and freq lock */
396 while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
397 ADPLLJ_STATUS_PHSFRQLOCK)
401 static void unlock_pll_control_mmr(void)
403 /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
404 writel(0x1EDA4C3D, 0x481C5040);
405 writel(0x2FF1AC2B, 0x48140060);
406 writel(0xF757FDC0, 0x48140064);
407 writel(0xE2BC3A6D, 0x48140068);
408 writel(0x1EBF131D, 0x4814006c);
409 writel(0x6F361E05, 0x48140070);
412 static void mpu_pll_config(void)
414 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
417 static void l3_pll_config(void)
419 u32 l3_osc_src, rd_osc_src = 0;
421 l3_osc_src = L3_OSC_SRC;
422 rd_osc_src = readl(OSC_SRC_CTRL);
424 if (OSC_SRC0 == l3_osc_src)
425 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
427 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
429 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
432 void ddr_pll_config(unsigned int ddrpll_m)
434 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
437 void sata_pll_config(void)
440 * This sequence for configuring the SATA PLL
441 * resident in the control module is documented
442 * in TI8148 TRM section 21.3.1
444 writel(SATA_PLLCFG1, &spll->pllcfg1);
447 writel(SATA_PLLCFG3, &spll->pllcfg3);
450 writel(SATA_PLLCFG0_1, &spll->pllcfg0);
453 writel(SATA_PLLCFG0_2, &spll->pllcfg0);
456 writel(SATA_PLLCFG0_3, &spll->pllcfg0);
459 writel(SATA_PLLCFG0_4, &spll->pllcfg0);
462 while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
466 void enable_emif_clocks(void) {};
468 void enable_dmm_clocks(void)
470 writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
471 writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
472 writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
473 while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
475 writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
476 while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
478 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
480 writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
481 while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
483 writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
484 while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
489 * Configure the PLL/PRCM for necessary peripherals
493 unlock_pll_control_mmr();
495 /* Enable the control module */
496 writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
503 /* Enable the required peripherals */