4 * Clocks for TI814X based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
26 #define PRCM_MOD_EN 0x2
32 #define L3_OSC_SRC OSC_SRC0
36 #define DCO_HS2_MIN 500
37 #define DCO_HS2_MAX 1000
38 #define DCO_HS1_MIN 1000
39 #define DCO_HS1_MAX 2000
41 #define SELFREQDCO_HS2 0x00000801
42 #define SELFREQDCO_HS1 0x00001001
47 #define MPU_CLKCTRL 0x1
52 #define L3_CLKCTRL 0x801
57 #define DDR_CLKCTRL 0x801
59 /* ADPLLJ register values */
60 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
61 #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
62 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
63 #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
64 #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
65 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
66 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
67 #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
68 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
69 #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
70 #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
71 #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
72 ADPLLJ_CLKCTRL_CLKOUTEN | \
73 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
74 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
76 #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
77 #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
78 #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
79 ADPLLJ_STATUS_FREQLOCK)
80 #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
81 #define ADPLLJ_STATUS_BYPASS (1 << 0)
82 #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
85 #define ADPLLJ_TENABLE_ENB (1 << 0)
86 #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
88 #define ADPLLJ_M2NDIV_M2SHIFT 16
90 #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
91 #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
92 #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
98 unsigned int tenablediv;
101 unsigned int fracdiv;
103 unsigned int fracctrl;
106 unsigned int rampctrl;
109 #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
112 #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
115 unsigned int resv0[2];
116 unsigned int l3fastclkstctrl;
117 unsigned int resv1[1];
118 unsigned int pciclkstctrl;
119 unsigned int resv2[1];
120 unsigned int ducaticlkstctrl;
121 unsigned int resv3[1];
122 unsigned int emif0clkctrl;
123 unsigned int emif1clkctrl;
124 unsigned int dmmclkctrl;
125 unsigned int fwclkctrl;
126 unsigned int resv4[10];
127 unsigned int usbclkctrl;
128 unsigned int resv5[1];
129 unsigned int sataclkctrl;
130 unsigned int resv6[4];
131 unsigned int ducaticlkctrl;
132 unsigned int pciclkctrl;
135 #define CM_ALWON_BASE (PRCM_BASE + 0x1400)
138 unsigned int l3slowclkstctrl;
139 unsigned int ethclkstctrl;
140 unsigned int l3medclkstctrl;
141 unsigned int mmu_clkstctrl;
142 unsigned int mmucfg_clkstctrl;
143 unsigned int ocmc0clkstctrl;
144 unsigned int vcpclkstctrl;
145 unsigned int mpuclkstctrl;
146 unsigned int sysclk4clkstctrl;
147 unsigned int sysclk5clkstctrl;
148 unsigned int sysclk6clkstctrl;
149 unsigned int rtcclkstctrl;
150 unsigned int l3fastclkstctrl;
151 unsigned int resv0[67];
152 unsigned int mcasp0clkctrl;
153 unsigned int mcasp1clkctrl;
154 unsigned int mcasp2clkctrl;
155 unsigned int mcbspclkctrl;
156 unsigned int uart0clkctrl;
157 unsigned int uart1clkctrl;
158 unsigned int uart2clkctrl;
159 unsigned int gpio0clkctrl;
160 unsigned int gpio1clkctrl;
161 unsigned int i2c0clkctrl;
162 unsigned int i2c1clkctrl;
163 unsigned int mcasp345clkctrl;
164 unsigned int atlclkctrl;
165 unsigned int mlbclkctrl;
166 unsigned int pataclkctrl;
167 unsigned int resv1[1];
168 unsigned int uart3clkctrl;
169 unsigned int uart4clkctrl;
170 unsigned int uart5clkctrl;
171 unsigned int wdtimerclkctrl;
172 unsigned int spiclkctrl;
173 unsigned int mailboxclkctrl;
174 unsigned int spinboxclkctrl;
175 unsigned int mmudataclkctrl;
176 unsigned int resv2[2];
177 unsigned int mmucfgclkctrl;
178 unsigned int resv3[2];
179 unsigned int ocmc0clkctrl;
180 unsigned int vcpclkctrl;
181 unsigned int resv4[2];
182 unsigned int controlclkctrl;
183 unsigned int resv5[2];
184 unsigned int gpmcclkctrl;
185 unsigned int ethernet0clkctrl;
186 unsigned int resv6[1];
187 unsigned int mpuclkctrl;
188 unsigned int debugssclkctrl;
189 unsigned int l3clkctrl;
190 unsigned int l4hsclkctrl;
191 unsigned int l4lsclkctrl;
192 unsigned int rtcclkctrl;
193 unsigned int tpccclkctrl;
194 unsigned int tptc0clkctrl;
195 unsigned int tptc1clkctrl;
196 unsigned int tptc2clkctrl;
197 unsigned int tptc3clkctrl;
198 unsigned int resv7[4];
199 unsigned int dcan01clkctrl;
200 unsigned int mmchs0clkctrl;
201 unsigned int mmchs1clkctrl;
202 unsigned int mmchs2clkctrl;
203 unsigned int custefuseclkctrl;
207 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
208 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
211 * Enable the peripheral clock for required peripherals
213 static void enable_per_clocks(void)
216 writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
217 while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
221 writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
222 while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
227 * select the HS1 or HS2 for DCO Freq
230 static u32 pll_dco_freq_sel(u32 clkout_dco)
232 if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
233 return SELFREQDCO_HS2;
234 else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
235 return SELFREQDCO_HS1;
241 * select the sigma delta config
242 * return: sigma delta val
244 static u32 pll_sigma_delta_val(u32 clkout_dco)
249 frac_div = (float) clkout_dco / 250;
250 frac_div = frac_div + 0.90;
251 sig_val = (int)frac_div;
252 sig_val = sig_val << 24;
258 * configure individual ADPLLJ
260 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
261 u32 clkctrl_val, int adpllj)
263 const struct ad_pll *adpll = (struct ad_pll *)base;
264 u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
265 u32 sig_val = 0, hs_mod = 0;
267 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
270 /* calculate clkout_dco */
271 clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
273 /* sigma delta & Hs mode selection skip for ADPLLS*/
275 sig_val = pll_sigma_delta_val(clkout_dco);
276 hs_mod = pll_dco_freq_sel(clkout_dco);
280 read_clkctrl = readl(&adpll->clkctrl);
281 writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
282 while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
283 != ADPLLJ_STATUS_BYPASSANDACK)
287 read_clkctrl = readl(&adpll->clkctrl);
288 writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
291 * ref_clk = 20/(n + 1);
292 * clkout_dco = ref_clk * m;
293 * clk_out = clkout_dco/m2;
295 read_clkctrl = readl(&adpll->clkctrl) &
296 ~(ADPLLJ_CLKCTRL_LPMODE |
297 ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
298 ADPLLJ_CLKCTRL_REGM4XEN);
299 writel(m2nval, &adpll->m2ndiv);
300 writel(mn2val, &adpll->mn2div);
302 /* Skip for modena(ADPLLS) */
304 writel(sig_val, &adpll->fracdiv);
305 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
308 /* Load M2, N2 dividers of ADPLL */
309 writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
310 writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
312 /* Load M, N dividers of ADPLL */
313 writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
314 writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
316 /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
317 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
319 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
322 /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
323 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
324 writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
326 /* Wait for phase and freq lock */
327 while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
328 ADPLLJ_STATUS_PHSFRQLOCK)
332 static void unlock_pll_control_mmr(void)
334 /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
335 writel(0x1EDA4C3D, 0x481C5040);
336 writel(0x2FF1AC2B, 0x48140060);
337 writel(0xF757FDC0, 0x48140064);
338 writel(0xE2BC3A6D, 0x48140068);
339 writel(0x1EBF131D, 0x4814006c);
340 writel(0x6F361E05, 0x48140070);
343 static void mpu_pll_config(void)
345 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
348 static void l3_pll_config(void)
350 u32 l3_osc_src, rd_osc_src = 0;
352 l3_osc_src = L3_OSC_SRC;
353 rd_osc_src = readl(OSC_SRC_CTRL);
355 if (OSC_SRC0 == l3_osc_src)
356 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
358 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
360 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
363 void ddr_pll_config(unsigned int ddrpll_m)
365 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
368 void enable_emif_clocks(void) {};
370 void enable_dmm_clocks(void)
372 writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
373 writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
374 writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
375 while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
377 writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
378 while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
380 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
382 writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
383 while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
385 writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
386 while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
391 * Configure the PLL/PRCM for necessary peripherals
395 unlock_pll_control_mmr();
397 /* Enable the control module */
398 writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
404 /* Enable the required peripherals */