4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
40 #ifdef CONFIG_SPL_BUILD
41 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
44 static const struct gpio_bank gpio_bank_am33xx[4] = {
45 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
46 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
47 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
48 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
51 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
53 /* MII mode defines */
54 #define MII_MODE_ENABLE 0x0
55 #define RGMII_MODE_ENABLE 0xA
57 /* GPIO that controls power to DDR on EVM-SK */
58 #define GPIO_DDR_VTT_EN 7
60 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
62 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
64 static inline int board_is_bone(void)
66 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
69 static inline int board_is_bone_lt(void)
71 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
74 static inline int board_is_evm_sk(void)
76 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
80 * Read header information from EEPROM into global structure.
82 static int read_eeprom(void)
84 /* Check if baseboard eeprom is available */
85 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
86 puts("Could not probe the EEPROM; something fundamentally "
87 "wrong on the I2C bus.\n");
91 /* read the eeprom using i2c */
92 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
94 puts("Could not read the EEPROM; something fundamentally"
95 " wrong on the I2C bus.\n");
99 if (header.magic != 0xEE3355AA) {
101 * read the eeprom using i2c again,
102 * but use only a 1 byte address
104 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
105 (uchar *)&header, sizeof(header))) {
106 puts("Could not read the EEPROM; something "
107 "fundamentally wrong on the I2C bus.\n");
111 if (header.magic != 0xEE3355AA) {
112 printf("Incorrect magic number (0x%x) in EEPROM\n",
121 #ifdef CONFIG_SPL_BUILD
123 #define UART_RESET (0x1 << 1)
124 #define UART_CLK_RUNNING_MASK 0x1
125 #define UART_SMART_IDLE_EN (0x1 << 0x3)
127 static void rtc32k_enable(void)
129 struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
132 * Unlock the RTC's registers. For more details please see the
133 * RTC_SS section of the TRM. In order to unlock we need to
134 * write these specific values (keys) in this order.
136 writel(0x83e70b13, &rtc->kick0r);
137 writel(0x95a4f1e0, &rtc->kick1r);
139 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
140 writel((1 << 3) | (1 << 6), &rtc->osc);
145 * Determine what type of DDR we have.
147 static short inline board_memory_type(void)
149 /* The following boards are known to use DDR3. */
150 if (board_is_evm_sk() || board_is_bone_lt())
151 return EMIF_REG_SDRAM_TYPE_DDR3;
153 return EMIF_REG_SDRAM_TYPE_DDR2;
157 * early system init of muxing and clocks.
161 /* WDT1 is already running when the bootloader gets control
162 * Disable it to avoid "random" resets
164 writel(0xAAAA, &wdtimer->wdtwspr);
165 while (readl(&wdtimer->wdtwwps) != 0x0)
167 writel(0x5555, &wdtimer->wdtwspr);
168 while (readl(&wdtimer->wdtwwps) != 0x0)
171 #ifdef CONFIG_SPL_BUILD
172 /* Setup the PLLs and the clocks for the peripherals */
175 /* Enable RTC32K clock */
181 enable_uart0_pin_mux();
183 regVal = readl(&uart_base->uartsyscfg);
184 regVal |= UART_RESET;
185 writel(regVal, &uart_base->uartsyscfg);
186 while ((readl(&uart_base->uartsyssts) &
187 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
190 /* Disable smart idle */
191 regVal = readl(&uart_base->uartsyscfg);
192 regVal |= UART_SMART_IDLE_EN;
193 writel(regVal, &uart_base->uartsyscfg);
197 preloader_console_init();
199 /* Initalize the board header */
200 enable_i2c0_pin_mux();
201 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
202 if (read_eeprom() < 0)
203 puts("Could not get board ID.\n");
205 enable_board_pin_mux(&header);
206 if (board_is_evm_sk()) {
208 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
209 * This is safe enough to do on older revs.
211 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
212 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
215 config_ddr(board_memory_type());
219 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
220 int board_mmc_init(bd_t *bis)
224 ret = omap_mmc_init(0, 0, 0);
228 return omap_mmc_init(1, 0, 0);
232 void setup_clocks_for_console(void)
234 /* Not yet implemented */
239 * Basic board specific setup. Pinmux has been handled already.
243 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
244 if (read_eeprom() < 0)
245 puts("Could not get board ID.\n");
247 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
252 #ifdef CONFIG_DRIVER_TI_CPSW
253 static void cpsw_control(int enabled)
255 /* VTP can be added here */
260 static struct cpsw_slave_data cpsw_slaves[] = {
262 .slave_reg_ofs = 0x208,
263 .sliver_reg_ofs = 0xd80,
267 .slave_reg_ofs = 0x308,
268 .sliver_reg_ofs = 0xdc0,
273 static struct cpsw_platform_data cpsw_data = {
274 .mdio_base = AM335X_CPSW_MDIO_BASE,
275 .cpsw_base = AM335X_CPSW_BASE,
278 .cpdma_reg_ofs = 0x800,
280 .slave_data = cpsw_slaves,
281 .ale_reg_ofs = 0xd00,
283 .host_port_reg_ofs = 0x108,
284 .hw_stats_reg_ofs = 0x900,
285 .mac_control = (1 << 5),
286 .control = cpsw_control,
288 .version = CPSW_CTRL_VERSION_2,
291 int board_eth_init(bd_t *bis)
294 uint32_t mac_hi, mac_lo;
296 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
297 debug("<ethaddr> not set. Reading from E-fuse\n");
298 /* try reading mac address from efuse */
299 mac_lo = readl(&cdev->macid0l);
300 mac_hi = readl(&cdev->macid0h);
301 mac_addr[0] = mac_hi & 0xFF;
302 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
303 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
304 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
305 mac_addr[4] = mac_lo & 0xFF;
306 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
308 if (is_valid_ether_addr(mac_addr))
309 eth_setenv_enetaddr("ethaddr", mac_addr);
314 if (board_is_bone() || board_is_bone_lt()) {
315 writel(MII_MODE_ENABLE, &cdev->miisel);
316 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
317 PHY_INTERFACE_MODE_MII;
319 writel(RGMII_MODE_ENABLE, &cdev->miisel);
320 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
321 PHY_INTERFACE_MODE_RGMII;
324 return cpsw_register(&cpsw_data);