4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/omap.h>
24 #include <asm/arch/ddr_defs.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/common_def.h>
30 #include <asm/omap_common.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
40 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
41 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 static const struct gpio_bank gpio_bank_am33xx[4] = {
44 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
45 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
46 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
47 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
50 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
52 /* MII mode defines */
53 #define MII_MODE_ENABLE 0x0
54 #define RGMII_MODE_ENABLE 0xA
56 /* GPIO that controls power to DDR on EVM-SK */
57 #define GPIO_DDR_VTT_EN 7
59 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
61 #define NO_OF_MAC_ADDR 3
65 struct am335x_baseboard_id {
71 char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
74 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
76 static inline int board_is_bone(void)
78 return !strncmp(header.name, "A335BONE", NAME_LEN);
81 static inline int board_is_evm_sk(void)
83 return !strncmp("A335X_SK", header.name, NAME_LEN);
87 * Read header information from EEPROM into global structure.
89 static int read_eeprom(void)
91 /* Check if baseboard eeprom is available */
92 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
93 puts("Could not probe the EEPROM; something fundamentally "
94 "wrong on the I2C bus.\n");
98 /* read the eeprom using i2c */
99 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
101 puts("Could not read the EEPROM; something fundamentally"
102 " wrong on the I2C bus.\n");
106 if (header.magic != 0xEE3355AA) {
108 * read the eeprom using i2c again,
109 * but use only a 1 byte address
111 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
112 (uchar *)&header, sizeof(header))) {
113 puts("Could not read the EEPROM; something "
114 "fundamentally wrong on the I2C bus.\n");
118 if (header.magic != 0xEE3355AA) {
119 printf("Incorrect magic number (0x%x) in EEPROM\n",
129 #ifdef CONFIG_SPL_BUILD
130 #define UART_RESET (0x1 << 1)
131 #define UART_CLK_RUNNING_MASK 0x1
132 #define UART_SMART_IDLE_EN (0x1 << 0x3)
135 #ifdef CONFIG_SPL_BUILD
136 /* Initialize timer */
137 static void init_timer(void)
139 /* Reset the Timer */
140 writel(0x2, (&timer_base->tscir));
142 /* Wait until the reset is done */
143 while (readl(&timer_base->tiocp_cfg) & 1)
146 /* Start the Timer */
147 writel(0x1, (&timer_base->tclr));
152 * Determine what type of DDR we have.
154 static short inline board_memory_type(void)
156 /* The following boards are known to use DDR3. */
157 if (board_is_evm_sk())
158 return EMIF_REG_SDRAM_TYPE_DDR3;
160 return EMIF_REG_SDRAM_TYPE_DDR2;
164 * early system init of muxing and clocks.
168 /* WDT1 is already running when the bootloader gets control
169 * Disable it to avoid "random" resets
171 writel(0xAAAA, &wdtimer->wdtwspr);
172 while (readl(&wdtimer->wdtwwps) != 0x0)
174 writel(0x5555, &wdtimer->wdtwspr);
175 while (readl(&wdtimer->wdtwwps) != 0x0)
178 #ifdef CONFIG_SPL_BUILD
179 /* Setup the PLLs and the clocks for the peripherals */
185 enable_uart0_pin_mux();
187 regVal = readl(&uart_base->uartsyscfg);
188 regVal |= UART_RESET;
189 writel(regVal, &uart_base->uartsyscfg);
190 while ((readl(&uart_base->uartsyssts) &
191 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
194 /* Disable smart idle */
195 regVal = readl(&uart_base->uartsyscfg);
196 regVal |= UART_SMART_IDLE_EN;
197 writel(regVal, &uart_base->uartsyscfg);
199 /* Initialize the Timer */
202 preloader_console_init();
204 /* Initalize the board header */
205 enable_i2c0_pin_mux();
206 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
207 if (read_eeprom() < 0)
208 puts("Could not get board ID.\n");
210 if (board_is_evm_sk()) {
212 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
213 * This is safe enough to do on older revs.
215 enable_gpio0_7_pin_mux();
216 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
217 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
220 config_ddr(board_memory_type());
224 enable_mmc0_pin_mux();
227 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
228 int board_mmc_init(bd_t *bis)
230 return omap_mmc_init(0, 0, 0);
234 void setup_clocks_for_console(void)
236 /* Not yet implemented */
241 * Basic board specific setup
245 enable_uart0_pin_mux();
247 enable_i2c0_pin_mux();
248 enable_i2c1_pin_mux();
249 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
250 if (read_eeprom() < 0)
251 puts("Could not get board ID.\n");
253 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
258 #ifdef CONFIG_DRIVER_TI_CPSW
259 static void cpsw_control(int enabled)
261 /* VTP can be added here */
266 static struct cpsw_slave_data cpsw_slaves[] = {
268 .slave_reg_ofs = 0x208,
269 .sliver_reg_ofs = 0xd80,
273 .slave_reg_ofs = 0x308,
274 .sliver_reg_ofs = 0xdc0,
279 static struct cpsw_platform_data cpsw_data = {
280 .mdio_base = AM335X_CPSW_MDIO_BASE,
281 .cpsw_base = AM335X_CPSW_BASE,
284 .cpdma_reg_ofs = 0x800,
286 .slave_data = cpsw_slaves,
287 .ale_reg_ofs = 0xd00,
289 .host_port_reg_ofs = 0x108,
290 .hw_stats_reg_ofs = 0x900,
291 .mac_control = (1 << 5),
292 .control = cpsw_control,
294 .version = CPSW_CTRL_VERSION_2,
297 int board_eth_init(bd_t *bis)
300 uint32_t mac_hi, mac_lo;
302 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
303 debug("<ethaddr> not set. Reading from E-fuse\n");
304 /* try reading mac address from efuse */
305 mac_lo = readl(&cdev->macid0l);
306 mac_hi = readl(&cdev->macid0h);
307 mac_addr[0] = mac_hi & 0xFF;
308 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
309 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
310 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
311 mac_addr[4] = mac_lo & 0xFF;
312 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
314 if (is_valid_ether_addr(mac_addr))
315 eth_setenv_enetaddr("ethaddr", mac_addr);
320 if (board_is_bone()) {
321 enable_mii1_pin_mux();
322 writel(MII_MODE_ENABLE, &cdev->miisel);
323 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
324 PHY_INTERFACE_MODE_MII;
326 enable_rgmii1_pin_mux();
327 writel(RGMII_MODE_ENABLE, &cdev->miisel);
328 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
329 PHY_INTERFACE_MODE_RGMII;
332 return cpsw_register(&cpsw_data);