4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
29 #include <asm/errno.h>
30 #include <linux/compiler.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/musb.h>
34 #include <asm/omap_musb.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 static const struct gpio_bank gpio_bank_am33xx[4] = {
39 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
40 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
41 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
42 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
45 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
47 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
48 int cpu_mmc_init(bd_t *bis)
52 ret = omap_mmc_init(0, 0, 0, -1, -1);
56 return omap_mmc_init(1, 0, 0, -1, -1);
60 /* AM33XX has two MUSB controllers which can be host or gadget */
61 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
62 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
63 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
65 /* USB 2.0 PHY Control */
66 #define CM_PHY_PWRDN (1 << 0)
67 #define CM_PHY_OTG_PWRDN (1 << 1)
68 #define OTGVDET_EN (1 << 19)
69 #define OTGSESSENDEN (1 << 20)
71 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
74 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
75 OTGVDET_EN | OTGSESSENDEN);
77 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
81 static struct musb_hdrc_config musb_config = {
88 #ifdef CONFIG_AM335X_USB0
89 static void am33xx_otg0_set_phy_power(u8 on)
91 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
94 struct omap_musb_board_data otg0_board_data = {
95 .set_phy_power = am33xx_otg0_set_phy_power,
98 static struct musb_hdrc_platform_data otg0_plat = {
99 .mode = CONFIG_AM335X_USB0_MODE,
100 .config = &musb_config,
102 .platform_ops = &musb_dsps_ops,
103 .board_data = &otg0_board_data,
107 #ifdef CONFIG_AM335X_USB1
108 static void am33xx_otg1_set_phy_power(u8 on)
110 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
113 struct omap_musb_board_data otg1_board_data = {
114 .set_phy_power = am33xx_otg1_set_phy_power,
117 static struct musb_hdrc_platform_data otg1_plat = {
118 .mode = CONFIG_AM335X_USB1_MODE,
119 .config = &musb_config,
121 .platform_ops = &musb_dsps_ops,
122 .board_data = &otg1_board_data,
127 int arch_misc_init(void)
129 #ifdef CONFIG_AM335X_USB0
130 musb_register(&otg0_plat, &otg0_board_data,
131 (void *)USB0_OTG_BASE);
133 #ifdef CONFIG_AM335X_USB1
134 musb_register(&otg1_plat, &otg1_board_data,
135 (void *)USB1_OTG_BASE);
140 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
142 * This function is the place to do per-board things such as ramp up the
143 * MPU clock frequency.
145 __weak void am33xx_spl_board_init(void)
149 static void rtc32k_enable(void)
151 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
154 * Unlock the RTC's registers. For more details please see the
155 * RTC_SS section of the TRM. In order to unlock we need to
156 * write these specific values (keys) in this order.
158 writel(0x83e70b13, &rtc->kick0r);
159 writel(0x95a4f1e0, &rtc->kick1r);
161 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
162 writel((1 << 3) | (1 << 6), &rtc->osc);
165 static void uart_soft_reset(void)
167 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
170 regval = readl(&uart_base->uartsyscfg);
171 regval |= UART_RESET;
172 writel(regval, &uart_base->uartsyscfg);
173 while ((readl(&uart_base->uartsyssts) &
174 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
177 /* Disable smart idle */
178 regval = readl(&uart_base->uartsyscfg);
179 regval |= UART_SMART_IDLE_EN;
180 writel(regval, &uart_base->uartsyscfg);
183 static void watchdog_disable(void)
185 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
187 writel(0xAAAA, &wdtimer->wdtwspr);
188 while (readl(&wdtimer->wdtwwps) != 0x0)
190 writel(0x5555, &wdtimer->wdtwspr);
191 while (readl(&wdtimer->wdtwwps) != 0x0)
199 * The ROM will only have set up sufficient pinmux to allow for the
200 * first 4KiB NOR to be read, we must finish doing what we know of
201 * the NOR mux in this space in order to continue.
203 #ifdef CONFIG_NOR_BOOT
204 enable_norboot_pin_mux();
207 * Save the boot parameters passed from romcode.
208 * We cannot delay the saving further than this,
209 * to prevent overwrites.
211 #ifdef CONFIG_SPL_BUILD
212 save_omap_boot_params();
214 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
218 setup_clocks_for_console();
221 #ifdef CONFIG_NOR_BOOT
222 gd->baudrate = CONFIG_BAUDRATE;
224 gd->have_console = 1;
227 preloader_console_init();
229 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
232 /* Enable RTC32K clock */