4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/omap.h>
24 #include <asm/arch/ddr_defs.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/common_def.h>
30 #include <asm/omap_common.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
40 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
41 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 static const struct gpio_bank gpio_bank_am33xx[4] = {
44 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
45 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
46 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
47 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
50 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
52 /* MII mode defines */
53 #define MII_MODE_ENABLE 0x0
54 #define RGMII_MODE_ENABLE 0xA
56 /* GPIO that controls power to DDR on EVM-SK */
57 #define GPIO_DDR_VTT_EN 7
59 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
62 * I2C Address of on-board EEPROM
64 #define I2C_BASE_BOARD_ADDR 0x50
66 #define NO_OF_MAC_ADDR 3
70 struct am335x_baseboard_id {
76 char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
79 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
81 static inline int board_is_bone(void)
83 return !strncmp(header.name, "A335BONE", NAME_LEN);
86 static inline int board_is_evm_sk(void)
88 return !strncmp("A335X_SK", header.name, NAME_LEN);
92 * Read header information from EEPROM into global structure.
94 static int read_eeprom(void)
96 /* Check if baseboard eeprom is available */
97 if (i2c_probe(I2C_BASE_BOARD_ADDR)) {
98 puts("Could not probe the EEPROM; something fundamentally "
99 "wrong on the I2C bus.\n");
103 /* read the eeprom using i2c */
104 if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 2, (uchar *)&header,
106 puts("Could not read the EEPROM; something fundamentally"
107 " wrong on the I2C bus.\n");
111 if (header.magic != 0xEE3355AA) {
113 * read the eeprom using i2c again,
114 * but use only a 1 byte address
116 if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 1, (uchar *)&header,
118 puts("Could not read the EEPROM; something "
119 "fundamentally wrong on the I2C bus.\n");
123 if (header.magic != 0xEE3355AA) {
124 printf("Incorrect magic number (0x%x) in EEPROM\n",
134 #ifdef CONFIG_SPL_BUILD
135 #define UART_RESET (0x1 << 1)
136 #define UART_CLK_RUNNING_MASK 0x1
137 #define UART_SMART_IDLE_EN (0x1 << 0x3)
140 #ifdef CONFIG_SPL_BUILD
141 /* Initialize timer */
142 static void init_timer(void)
144 /* Reset the Timer */
145 writel(0x2, (&timer_base->tscir));
147 /* Wait until the reset is done */
148 while (readl(&timer_base->tiocp_cfg) & 1)
151 /* Start the Timer */
152 writel(0x1, (&timer_base->tclr));
157 * Determine what type of DDR we have.
159 static short inline board_memory_type(void)
161 /* The following boards are known to use DDR3. */
162 if (board_is_evm_sk())
163 return EMIF_REG_SDRAM_TYPE_DDR3;
165 return EMIF_REG_SDRAM_TYPE_DDR2;
169 * early system init of muxing and clocks.
173 /* WDT1 is already running when the bootloader gets control
174 * Disable it to avoid "random" resets
176 writel(0xAAAA, &wdtimer->wdtwspr);
177 while (readl(&wdtimer->wdtwwps) != 0x0)
179 writel(0x5555, &wdtimer->wdtwspr);
180 while (readl(&wdtimer->wdtwwps) != 0x0)
183 #ifdef CONFIG_SPL_BUILD
184 /* Setup the PLLs and the clocks for the peripherals */
190 enable_uart0_pin_mux();
192 regVal = readl(&uart_base->uartsyscfg);
193 regVal |= UART_RESET;
194 writel(regVal, &uart_base->uartsyscfg);
195 while ((readl(&uart_base->uartsyssts) &
196 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
199 /* Disable smart idle */
200 regVal = readl(&uart_base->uartsyscfg);
201 regVal |= UART_SMART_IDLE_EN;
202 writel(regVal, &uart_base->uartsyscfg);
204 /* Initialize the Timer */
207 preloader_console_init();
209 /* Initalize the board header */
210 enable_i2c0_pin_mux();
211 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
212 if (read_eeprom() < 0)
213 puts("Could not get board ID.\n");
215 if (board_is_evm_sk()) {
217 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
218 * This is safe enough to do on older revs.
220 enable_gpio0_7_pin_mux();
221 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
222 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
225 config_ddr(board_memory_type());
229 enable_mmc0_pin_mux();
232 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
233 int board_mmc_init(bd_t *bis)
235 return omap_mmc_init(0, 0, 0);
239 void setup_clocks_for_console(void)
241 /* Not yet implemented */
246 * Basic board specific setup
250 enable_uart0_pin_mux();
252 enable_i2c0_pin_mux();
253 enable_i2c1_pin_mux();
254 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
255 if (read_eeprom() < 0)
256 puts("Could not get board ID.\n");
258 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
263 #ifdef CONFIG_DRIVER_TI_CPSW
264 static void cpsw_control(int enabled)
266 /* VTP can be added here */
271 static struct cpsw_slave_data cpsw_slaves[] = {
273 .slave_reg_ofs = 0x208,
274 .sliver_reg_ofs = 0xd80,
278 .slave_reg_ofs = 0x308,
279 .sliver_reg_ofs = 0xdc0,
284 static struct cpsw_platform_data cpsw_data = {
285 .mdio_base = AM335X_CPSW_MDIO_BASE,
286 .cpsw_base = AM335X_CPSW_BASE,
289 .cpdma_reg_ofs = 0x800,
291 .slave_data = cpsw_slaves,
292 .ale_reg_ofs = 0xd00,
294 .host_port_reg_ofs = 0x108,
295 .hw_stats_reg_ofs = 0x900,
296 .mac_control = (1 << 5),
297 .control = cpsw_control,
299 .version = CPSW_CTRL_VERSION_2,
302 int board_eth_init(bd_t *bis)
305 uint32_t mac_hi, mac_lo;
307 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
308 debug("<ethaddr> not set. Reading from E-fuse\n");
309 /* try reading mac address from efuse */
310 mac_lo = readl(&cdev->macid0l);
311 mac_hi = readl(&cdev->macid0h);
312 mac_addr[0] = mac_hi & 0xFF;
313 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
314 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
315 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
316 mac_addr[4] = mac_lo & 0xFF;
317 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
319 if (is_valid_ether_addr(mac_addr))
320 eth_setenv_enetaddr("ethaddr", mac_addr);
325 if (board_is_bone()) {
326 enable_mii1_pin_mux();
327 writel(MII_MODE_ENABLE, &cdev->miisel);
328 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
329 PHY_INTERFACE_MODE_MII;
331 enable_rgmii1_pin_mux();
332 writel(RGMII_MODE_ENABLE, &cdev->miisel);
333 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
334 PHY_INTERFACE_MODE_RGMII;
337 return cpsw_register(&cpsw_data);