4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/common_def.h>
29 #include <asm/omap_common.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
34 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
35 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
37 static const struct gpio_bank gpio_bank_am33xx[4] = {
38 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
39 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
40 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
41 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
44 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
47 #ifdef CONFIG_SPL_BUILD
48 #define UART_RESET (0x1 << 1)
49 #define UART_CLK_RUNNING_MASK 0x1
50 #define UART_SMART_IDLE_EN (0x1 << 0x3)
53 #ifdef CONFIG_SPL_BUILD
54 /* Initialize timer */
55 static void init_timer(void)
58 writel(0x2, (&timer_base->tscir));
60 /* Wait until the reset is done */
61 while (readl(&timer_base->tiocp_cfg) & 1)
65 writel(0x1, (&timer_base->tclr));
70 * early system init of muxing and clocks.
74 /* WDT1 is already running when the bootloader gets control
75 * Disable it to avoid "random" resets
77 writel(0xAAAA, &wdtimer->wdtwspr);
78 while (readl(&wdtimer->wdtwwps) != 0x0)
80 writel(0x5555, &wdtimer->wdtwspr);
81 while (readl(&wdtimer->wdtwwps) != 0x0)
84 #ifdef CONFIG_SPL_BUILD
85 /* Setup the PLLs and the clocks for the peripherals */
91 enable_uart0_pin_mux();
93 regVal = readl(&uart_base->uartsyscfg);
95 writel(regVal, &uart_base->uartsyscfg);
96 while ((readl(&uart_base->uartsyssts) &
97 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
100 /* Disable smart idle */
101 regVal = readl(&uart_base->uartsyscfg);
102 regVal |= UART_SMART_IDLE_EN;
103 writel(regVal, &uart_base->uartsyscfg);
105 /* Initialize the Timer */
108 preloader_console_init();
114 enable_mmc0_pin_mux();
117 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
118 int board_mmc_init(bd_t *bis)
120 return omap_mmc_init(0, 0, 0);
124 void setup_clocks_for_console(void)
126 /* Not yet implemented */