4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
29 #include <asm/errno.h>
30 #include <linux/compiler.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/musb.h>
34 #include <asm/omap_musb.h>
35 #include <asm/davinci_rtc.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static const struct gpio_bank gpio_bank_am33xx[4] = {
40 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
41 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
42 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
43 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
46 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
48 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
49 int cpu_mmc_init(bd_t *bis)
53 ret = omap_mmc_init(0, 0, 0, -1, -1);
57 return omap_mmc_init(1, 0, 0, -1, -1);
61 /* AM33XX has two MUSB controllers which can be host or gadget */
62 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
63 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
64 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
66 /* USB 2.0 PHY Control */
67 #define CM_PHY_PWRDN (1 << 0)
68 #define CM_PHY_OTG_PWRDN (1 << 1)
69 #define OTGVDET_EN (1 << 19)
70 #define OTGSESSENDEN (1 << 20)
72 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
75 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
76 OTGVDET_EN | OTGSESSENDEN);
78 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
82 static struct musb_hdrc_config musb_config = {
89 #ifdef CONFIG_AM335X_USB0
90 static void am33xx_otg0_set_phy_power(u8 on)
92 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
95 struct omap_musb_board_data otg0_board_data = {
96 .set_phy_power = am33xx_otg0_set_phy_power,
99 static struct musb_hdrc_platform_data otg0_plat = {
100 .mode = CONFIG_AM335X_USB0_MODE,
101 .config = &musb_config,
103 .platform_ops = &musb_dsps_ops,
104 .board_data = &otg0_board_data,
108 #ifdef CONFIG_AM335X_USB1
109 static void am33xx_otg1_set_phy_power(u8 on)
111 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
114 struct omap_musb_board_data otg1_board_data = {
115 .set_phy_power = am33xx_otg1_set_phy_power,
118 static struct musb_hdrc_platform_data otg1_plat = {
119 .mode = CONFIG_AM335X_USB1_MODE,
120 .config = &musb_config,
122 .platform_ops = &musb_dsps_ops,
123 .board_data = &otg1_board_data,
128 int arch_misc_init(void)
130 #ifdef CONFIG_AM335X_USB0
131 musb_register(&otg0_plat, &otg0_board_data,
132 (void *)USB0_OTG_BASE);
134 #ifdef CONFIG_AM335X_USB1
135 musb_register(&otg1_plat, &otg1_board_data,
136 (void *)USB1_OTG_BASE);
141 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
143 * This function is the place to do per-board things such as ramp up the
144 * MPU clock frequency.
146 __weak void am33xx_spl_board_init(void)
148 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
149 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
152 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
153 static void rtc32k_enable(void)
155 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
158 * Unlock the RTC's registers. For more details please see the
159 * RTC_SS section of the TRM. In order to unlock we need to
160 * write these specific values (keys) in this order.
162 writel(RTC_KICK0R_WE, &rtc->kick0r);
163 writel(RTC_KICK1R_WE, &rtc->kick1r);
165 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
166 writel((1 << 3) | (1 << 6), &rtc->osc);
170 static void uart_soft_reset(void)
172 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
175 regval = readl(&uart_base->uartsyscfg);
176 regval |= UART_RESET;
177 writel(regval, &uart_base->uartsyscfg);
178 while ((readl(&uart_base->uartsyssts) &
179 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
182 /* Disable smart idle */
183 regval = readl(&uart_base->uartsyscfg);
184 regval |= UART_SMART_IDLE_EN;
185 writel(regval, &uart_base->uartsyscfg);
188 static void watchdog_disable(void)
190 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
192 writel(0xAAAA, &wdtimer->wdtwspr);
193 while (readl(&wdtimer->wdtwwps) != 0x0)
195 writel(0x5555, &wdtimer->wdtwspr);
196 while (readl(&wdtimer->wdtwwps) != 0x0)
204 * The ROM will only have set up sufficient pinmux to allow for the
205 * first 4KiB NOR to be read, we must finish doing what we know of
206 * the NOR mux in this space in order to continue.
208 #ifdef CONFIG_NOR_BOOT
209 enable_norboot_pin_mux();
212 * Save the boot parameters passed from romcode.
213 * We cannot delay the saving further than this,
214 * to prevent overwrites.
216 #ifdef CONFIG_SPL_BUILD
217 save_omap_boot_params();
219 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
223 setup_clocks_for_console();
226 #ifdef CONFIG_NOR_BOOT
227 gd->baudrate = CONFIG_BAUDRATE;
229 gd->have_console = 1;
232 preloader_console_init();
234 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
237 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
238 /* Enable RTC32K clock */
245 #ifndef CONFIG_SYS_DCACHE_OFF
246 void enable_caches(void)
248 /* Enable D-cache. I-cache is already enabled in start.S */
251 #endif /* !CONFIG_SYS_DCACHE_OFF */