1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for ARM926EJS CPU-core
5 * Copyright (c) 2003 Texas Instruments
7 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
9 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
10 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
11 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
12 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
13 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
17 #include <asm-offsets.h>
22 *************************************************************************
24 * Startup Code (reset vector)
26 * do important init only if we don't start from memory!
27 * setup Memory and board specific bits prior to relocation.
28 * relocate armboot to ram
31 *************************************************************************
38 * set the cpu to SVC32 mode
46 * we do sys-critical inits only at reboot,
47 * not when booting from ram!
49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
55 /*------------------------------------------------------------------------------*/
57 .globl c_runtime_cpu_setup
63 *************************************************************************
65 * CPU_init_critical registers
67 * setup important registers
70 *************************************************************************
72 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
75 * flush D cache before disabling it
79 mrc p15, 0, r15, c7, c10, 3
82 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
83 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
86 * disable MMU and D cache
87 * enable I cache if SYS_ICACHE_OFF is not defined
89 mrc p15, 0, r0, c1, c0, 0
90 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
91 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
92 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
93 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
95 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
97 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
98 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
99 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
101 mcr p15, 0, r0, c1, c0, 0
103 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
105 * Go setup Memory and board specific bits prior to relocation.
107 mov r4, lr /* perserve link reg across call */
108 bl lowlevel_init /* go setup pll,mux,memory */
109 mov lr, r4 /* restore link */
111 mov pc, lr /* back to my caller */
112 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */