1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/spr_defs.h>
15 #include <asm/arch/spr_misc.h>
16 #include <asm/arch/spr_syscntl.h>
17 #include <linux/mtd/st_smi.h>
19 static void ddr_clock_init(void)
21 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
24 clkenb = readl(&misc_p->periph1_clken);
25 clkenb &= ~PERIPH_MPMCMSK;
26 clkenb |= PERIPH_MPMC_WE;
28 /* Intentionally done twice */
29 writel(clkenb, &misc_p->periph1_clken);
30 writel(clkenb, &misc_p->periph1_clken);
32 ddrpll = readl(&misc_p->pll_ctr_reg);
33 ddrpll &= ~MEM_CLK_SEL_MSK;
35 ddrpll |= MEM_CLK_HCLK;
36 #elif (CONFIG_DDR_2HCLK)
37 ddrpll |= MEM_CLK_2HCLK;
38 #elif (CONFIG_DDR_PLL2)
39 ddrpll |= MEM_CLK_PLL2;
41 #error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
43 writel(ddrpll, &misc_p->pll_ctr_reg);
45 writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
46 &misc_p->periph1_clken);
49 static void mpmc_init_values(void)
52 u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
53 u32 *mpmc_val_p = &mpmc_conf_vals[0];
55 for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
56 writel(*mpmc_val_p, mpmc_reg_p);
58 mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
61 * MPMC controller start
62 * MPMC waiting for DLLLOCKREG high
64 writel(0x01000100, &mpmc_reg_p[7]);
66 while (!(readl(&mpmc_reg_p[3]) & 0x10000))
70 static void mpmc_init(void)
72 /* Clock related settings for DDR */
76 * DDR pad register bits are different for different SoCs
77 * Compensation values are also handled separately
81 /* Initialize mpmc register values */
85 static void pll_init(void)
87 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
90 writel(FREQ_332, &misc_p->pll1_frq);
91 writel(0x1C0A, &misc_p->pll1_cntl);
92 writel(0x1C0E, &misc_p->pll1_cntl);
93 writel(0x1C06, &misc_p->pll1_cntl);
94 writel(0x1C0E, &misc_p->pll1_cntl);
96 writel(FREQ_332, &misc_p->pll2_frq);
97 writel(0x1C0A, &misc_p->pll2_cntl);
98 writel(0x1C0E, &misc_p->pll2_cntl);
99 writel(0x1C06, &misc_p->pll2_cntl);
100 writel(0x1C0E, &misc_p->pll2_cntl);
102 /* wait for pll locks */
103 while (!(readl(&misc_p->pll1_cntl) & 0x1))
105 while (!(readl(&misc_p->pll2_cntl) & 0x1))
109 static void mac_init(void)
111 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
113 writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
114 &misc_p->periph1_clken);
116 writel(SYNTH23, &misc_p->gmac_synth_clk);
118 switch (get_socrev()) {
119 case SOC_SPEAR600_AA:
120 case SOC_SPEAR600_AB:
121 case SOC_SPEAR600_BA:
122 case SOC_SPEAR600_BB:
123 case SOC_SPEAR600_BC:
124 case SOC_SPEAR600_BD:
125 writel(0x0, &misc_p->gmac_ctr_reg);
131 writel(0x4, &misc_p->gmac_ctr_reg);
135 writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
136 &misc_p->periph1_clken);
138 writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
139 &misc_p->periph1_rst);
140 writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
141 &misc_p->periph1_rst);
144 static void sys_init(void)
146 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
147 struct syscntl_regs *syscntl_p =
148 (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
150 /* Set system state to SLOW */
151 writel(SLOW, &syscntl_p->scctrl);
152 writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
154 /* Initialize PLLs */
158 * Ethernet configuration
159 * To be done only if the tftp boot is not selected already
160 * Boot code ensures the correct configuration in tftp booting
162 if (!tftp_boot_selected())
165 writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
166 writel(0x555, &misc_p->amba_clk_cfg);
168 writel(NORMAL, &syscntl_p->scctrl);
170 /* Wait for system to switch to normal mode */
171 while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
180 * @return SOC_SPEARXXX
184 #if defined(CONFIG_SPEAR600)
185 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
186 u32 soc_id = readl(&misc_p->soc_core_id);
187 u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
188 u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
190 if ((pri_socid == 'B') && (sec_socid == 'B'))
191 return SOC_SPEAR600_BB;
192 else if ((pri_socid == 'B') && (sec_socid == 'C'))
193 return SOC_SPEAR600_BC;
194 else if ((pri_socid == 'B') && (sec_socid == 'D'))
195 return SOC_SPEAR600_BD;
196 else if (soc_id == 0)
197 return SOC_SPEAR600_BA;
200 #elif defined(CONFIG_SPEAR300)
202 #elif defined(CONFIG_SPEAR310)
204 #elif defined(CONFIG_SPEAR320)
210 * SNOR (Serial NOR flash) related functions
212 static void snor_init(void)
214 struct smi_regs *const smicntl =
215 (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
217 /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
218 writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
222 u32 spl_boot_device(void)
226 /* Currently only SNOR is supported as the only */
227 if (snor_boot_selected()) {
228 /* SNOR-SMI initialization */
231 mode = BOOT_DEVICE_NOR;
237 void board_init_f(ulong dummy)
239 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
241 /* Initialize PLLs */
244 preloader_console_init();
247 /* Enable IPs (release reset) */
248 writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
250 /* Initialize MPMC */
251 puts("Configure DDR\n");
255 board_init_r(NULL, 0);