2 * (C) Copyright 2000-2009
3 * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/hardware.h>
12 #include <asm/arch/spr_misc.h>
13 #include <asm/arch/spr_defs.h>
15 void spear_late_init(void)
17 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
19 writel(0x80000007, &misc_p->arb_icm_ml1);
20 writel(0x80000007, &misc_p->arb_icm_ml2);
21 writel(0x80000007, &misc_p->arb_icm_ml3);
22 writel(0x80000007, &misc_p->arb_icm_ml4);
23 writel(0x80000007, &misc_p->arb_icm_ml5);
24 writel(0x80000007, &misc_p->arb_icm_ml6);
25 writel(0x80000007, &misc_p->arb_icm_ml7);
26 writel(0x80000007, &misc_p->arb_icm_ml8);
27 writel(0x80000007, &misc_p->arb_icm_ml9);
30 static void sel_1v8(void)
32 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
35 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
38 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
40 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
43 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
45 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
49 static void sel_2v5(void)
51 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
54 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
57 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
59 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
62 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
64 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
71 void plat_ddr_init(void)
73 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
75 u32 core3v3, ddr1v8, ddr2v5;
77 /* DDR pad register configurations */
78 ddrpad = readl(&misc_p->ddr_pad);
79 ddrpad &= ~DDR_PAD_CNF_MSK;
83 #elif (CONFIG_DDR_2HCLK)
85 #elif (CONFIG_DDR_PLL2)
88 writel(ddrpad, &misc_p->ddr_pad);
90 /* Compensation register configurations */
91 core3v3 = readl(&misc_p->core_3v3_compensation);
92 core3v3 &= 0x8080ffe0;
93 core3v3 |= 0x78000002;
94 writel(core3v3, &misc_p->core_3v3_compensation);
96 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
99 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
101 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
102 ddr2v5 &= 0x8080ffc0;
103 ddr2v5 |= 0x78000004;
104 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
106 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
107 /* Software memory configuration */
108 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
113 /* Hardware memory configuration */
114 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
124 * return true if the particular booting option is selected
125 * return false otherwise
127 static u32 read_bootstrap(void)
129 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
130 & CONFIG_SPEAR_BOOTSTRAPMASK;
133 int snor_boot_selected(void)
135 u32 bootstrap = read_bootstrap();
137 if (SNOR_BOOT_SUPPORTED) {
138 /* Check whether SNOR boot is selected */
139 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
140 CONFIG_SPEAR_ONLYSNORBOOT)
143 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
144 CONFIG_SPEAR_NORNAND8BOOT)
147 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
148 CONFIG_SPEAR_NORNAND16BOOT)
155 int nand_boot_selected(void)
157 u32 bootstrap = read_bootstrap();
159 if (NAND_BOOT_SUPPORTED) {
160 /* Check whether NAND boot is selected */
161 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
162 CONFIG_SPEAR_NORNAND8BOOT)
165 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
166 CONFIG_SPEAR_NORNAND16BOOT)
173 int pnor_boot_selected(void)
175 /* Parallel NOR boot is not selected in any SPEAr600 revision */
179 int usb_boot_selected(void)
181 u32 bootstrap = read_bootstrap();
183 if (USB_BOOT_SUPPORTED) {
184 /* Check whether USB boot is selected */
185 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
192 int tftp_boot_selected(void)
194 /* TFTP boot is not selected in any SPEAr600 revision */
198 int uart_boot_selected(void)
200 /* UART boot is not selected in any SPEAr600 revision */
204 int spi_boot_selected(void)
206 /* SPI boot is not selected in any SPEAr600 revision */
210 int i2c_boot_selected(void)
212 /* I2C boot is not selected in any SPEAr600 revision */
216 int mmc_boot_selected(void)
221 void plat_late_init(void)