3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/pantheon.h>
31 * Refer 6.2.9 in Datasheet
33 struct panthtmr_registers {
34 u32 clk_ctrl; /* Timer clk control reg */
35 u32 match[9]; /* Timer match registers */
36 u32 count[3]; /* Timer count registers */
39 u32 preload[3]; /* Timer preload value */
47 u32 cer; /* Timer count enable reg */
56 #define TIMER 0 /* Use TIMER 0 */
57 /* Each timer has 3 match registers */
58 #define MATCH_CMP(x) ((3 * TIMER) + x)
59 #define TIMER_LOAD_VAL 0xffffffff
60 #define COUNT_RD_REQ 0x1
62 DECLARE_GLOBAL_DATA_PTR;
63 /* Using gd->tbu from timestamp and gd->tbl for lastdec */
66 * For preventing risk of instability in reading counter value,
67 * first set read request to register cvwr and then read same
68 * register after it captures counter value.
70 ulong read_timer(void)
72 struct panthtmr_registers *panthtimers =
73 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
74 volatile int loop=100;
77 writel(COUNT_RD_REQ, &panthtimers->cvwr);
79 val = readl(&panthtimers->cvwr);
82 * This stop gcc complain and prevent loop mistake init to 0
84 val = readl(&panthtimers->cvwr);
89 ulong get_timer_masked(void)
91 ulong now = read_timer();
95 gd->tbu += now - gd->tbl;
97 /* we have an overflow ... */
98 gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
105 ulong get_timer(ulong base)
107 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
111 void __udelay(unsigned long usec)
116 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
117 endtime = get_timer_masked() + delayticks;
119 while (get_timer_masked() < endtime)
128 struct panthapb_registers *apb1clkres =
129 (struct panthapb_registers *) PANTHEON_APBC_BASE;
130 struct panthtmr_registers *panthtimers =
131 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
133 /* Enable Timer clock at 3.25 MHZ */
134 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
136 /* load value into timer */
137 writel(0x0, &panthtimers->clk_ctrl);
138 /* Use Timer 0 Match Resiger 0 */
139 writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
140 /* Preload value is 0 */
141 writel(0x0, &panthtimers->preload[TIMER]);
142 /* Enable match comparator 0 for Timer 0 */
143 writel(0x1, &panthtimers->preload_ctrl[TIMER]);
146 writel(0x1, &panthtimers->cer);
147 /* init the gd->tbu and gd->tbl value */
148 gd->tbl = read_timer();
154 #define MPMU_APRR_WDTR (1<<4)
155 #define TMR_WFAR 0xbaba /* WDT Register First key */
156 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
159 * This function uses internal Watchdog Timer
160 * based reset mechanism.
161 * Steps to write watchdog registers (protected access)
162 * 1. Write key value to TMR_WFAR reg.
163 * 2. Write key value to TMP_WSAR reg.
164 * 3. Perform write operation.
166 void reset_cpu (unsigned long ignored)
168 struct panthmpmu_registers *mpmu =
169 (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
170 struct panthtmr_registers *panthtimers =
171 (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
174 /* negate hardware reset to the WDT after system reset */
175 val = readl(&mpmu->aprr);
176 val = val | MPMU_APRR_WDTR;
177 writel(val, &mpmu->aprr);
179 /* reset/enable WDT clock */
180 writel(APBC_APBCLK, &mpmu->wdtpcr);
182 /* clear previous WDT status */
183 writel(TMR_WFAR, &panthtimers->wfar);
184 writel(TMP_WSAR, &panthtimers->wsar);
185 writel(0, &panthtimers->wdt_sts);
187 /* set match counter */
188 writel(TMR_WFAR, &panthtimers->wfar);
189 writel(TMP_WSAR, &panthtimers->wsar);
190 writel(0xf, &panthtimers->wdt_match_r);
192 /* enable WDT reset */
193 writel(TMR_WFAR, &panthtimers->wfar);
194 writel(TMP_WSAR, &panthtimers->wsar);
195 writel(0x3, &panthtimers->wdt_match_en);
197 /*enable functional WDT clock */
198 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
202 * This function is derived from PowerPC code (read timebase as long long).
203 * On ARM it just returns the timer value.
205 unsigned long long get_ticks(void)
211 * This function is derived from PowerPC code (timebase clock frequency).
212 * On ARM it returns the number of timer ticks per second.
214 ulong get_tbclk (void)
216 return (ulong)CONFIG_SYS_HZ;