3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/pantheon.h>
15 * Refer 6.2.9 in Datasheet
17 struct panthtmr_registers {
18 u32 clk_ctrl; /* Timer clk control reg */
19 u32 match[9]; /* Timer match registers */
20 u32 count[3]; /* Timer count registers */
23 u32 preload[3]; /* Timer preload value */
31 u32 cer; /* Timer count enable reg */
40 #define TIMER 0 /* Use TIMER 0 */
41 /* Each timer has 3 match registers */
42 #define MATCH_CMP(x) ((3 * TIMER) + x)
43 #define TIMER_LOAD_VAL 0xffffffff
44 #define COUNT_RD_REQ 0x1
46 DECLARE_GLOBAL_DATA_PTR;
47 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
50 * For preventing risk of instability in reading counter value,
51 * first set read request to register cvwr and then read same
52 * register after it captures counter value.
54 ulong read_timer(void)
56 struct panthtmr_registers *panthtimers =
57 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
58 volatile int loop=100;
61 writel(COUNT_RD_REQ, &panthtimers->cvwr);
63 val = readl(&panthtimers->cvwr);
66 * This stop gcc complain and prevent loop mistake init to 0
68 val = readl(&panthtimers->cvwr);
73 ulong get_timer_masked(void)
75 ulong now = read_timer();
77 if (now >= gd->arch.tbl) {
79 gd->arch.tbu += now - gd->arch.tbl;
81 /* we have an overflow ... */
82 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
89 ulong get_timer(ulong base)
91 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
95 void __udelay(unsigned long usec)
100 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
101 endtime = get_timer_masked() + delayticks;
103 while (get_timer_masked() < endtime)
112 struct panthapb_registers *apb1clkres =
113 (struct panthapb_registers *) PANTHEON_APBC_BASE;
114 struct panthtmr_registers *panthtimers =
115 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
117 /* Enable Timer clock at 3.25 MHZ */
118 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
120 /* load value into timer */
121 writel(0x0, &panthtimers->clk_ctrl);
122 /* Use Timer 0 Match Resiger 0 */
123 writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
124 /* Preload value is 0 */
125 writel(0x0, &panthtimers->preload[TIMER]);
126 /* Enable match comparator 0 for Timer 0 */
127 writel(0x1, &panthtimers->preload_ctrl[TIMER]);
130 writel(0x1, &panthtimers->cer);
131 /* init the gd->arch.tbu and gd->arch.tbl value */
132 gd->arch.tbl = read_timer();
138 #define MPMU_APRR_WDTR (1<<4)
139 #define TMR_WFAR 0xbaba /* WDT Register First key */
140 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
143 * This function uses internal Watchdog Timer
144 * based reset mechanism.
145 * Steps to write watchdog registers (protected access)
146 * 1. Write key value to TMR_WFAR reg.
147 * 2. Write key value to TMP_WSAR reg.
148 * 3. Perform write operation.
150 void reset_cpu (unsigned long ignored)
152 struct panthmpmu_registers *mpmu =
153 (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
154 struct panthtmr_registers *panthtimers =
155 (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
158 /* negate hardware reset to the WDT after system reset */
159 val = readl(&mpmu->aprr);
160 val = val | MPMU_APRR_WDTR;
161 writel(val, &mpmu->aprr);
163 /* reset/enable WDT clock */
164 writel(APBC_APBCLK, &mpmu->wdtpcr);
166 /* clear previous WDT status */
167 writel(TMR_WFAR, &panthtimers->wfar);
168 writel(TMP_WSAR, &panthtimers->wsar);
169 writel(0, &panthtimers->wdt_sts);
171 /* set match counter */
172 writel(TMR_WFAR, &panthtimers->wfar);
173 writel(TMP_WSAR, &panthtimers->wsar);
174 writel(0xf, &panthtimers->wdt_match_r);
176 /* enable WDT reset */
177 writel(TMR_WFAR, &panthtimers->wfar);
178 writel(TMP_WSAR, &panthtimers->wsar);
179 writel(0x3, &panthtimers->wdt_match_en);
181 /*enable functional WDT clock */
182 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
186 * This function is derived from PowerPC code (read timebase as long long).
187 * On ARM it just returns the timer value.
189 unsigned long long get_ticks(void)
195 * This function is derived from PowerPC code (timebase clock frequency).
196 * On ARM it returns the number of timer ticks per second.
198 ulong get_tbclk (void)
200 return (ulong)CONFIG_SYS_HZ;