1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for ARM926EJS CPU-core
5 * Copyright (c) 2003 Texas Instruments
7 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
9 * Copyright (c) 2001 Marius Groger <mag@sysgo.de>
10 * Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
11 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
12 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
13 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
16 * Change to support call back into iMX28 bootrom
17 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
18 * on behalf of DENX Software Engineering GmbH
21 #include <asm-offsets.h>
26 *************************************************************************
28 * Startup Code (reset vector)
30 * do important init only if we don't start from memory!
31 * setup Memory and board specific bits prior to relocation.
32 * relocate armboot to ram
35 *************************************************************************
41 * If the CPU is configured in "Wait JTAG connection mode", the stack
42 * pointer is not configured and is zero. This will cause crash when
43 * trying to push data onto stack right below here. Load the SP and make
44 * it point to the end of OCRAM if the SP is zero.
47 ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
50 * Store all registers on old stack pointer, this will allow us later to
51 * return to the BootROM and let the BootROM load U-Boot into RAM.
53 * WARNING: Register r0 and r1 are used by the BootROM to pass data
54 * to the called code. Register r0 will contain arbitrary
55 * data that are set in the BootStream. In case this code
56 * was started with CALL instruction, register r1 will contain
57 * pointer to the return value this function can then set.
58 * The code below MUST NOT CHANGE register r0 and r1 !
62 /* Save control register c1 */
63 mrc p15, 0, r2, c1, c0, 0
66 /* Set the cpu to SVC32 mode and store old CPSR register content. */
75 /* Restore BootROM's CPU mode (especially FIQ). */
80 * Restore c1 register. Especially set exception vector location
81 * back to BootROM space which is required by bootrom for USB boot.
84 mcr p15, 0, r2, c1, c0, 0
89 * In case this code was started by the CALL instruction, the register
90 * r0 is examined by the BootROM after this code returns. The value in
91 * r0 must be set to 0 to indicate successful return.