2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 /* 1 second delay should be plenty of time for block reset. */
42 #define RESET_MAX_TIMEOUT 1000000
44 #define MX28_BLOCK_SFTRST (1 << 31)
45 #define MX28_BLOCK_CLKGATE (1 << 30)
47 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
48 inline void lowlevel_init(void) {}
50 void reset_cpu(ulong ignored) __attribute__((noreturn));
52 void reset_cpu(ulong ignored)
54 struct mx28_rtc_regs *rtc_regs =
55 (struct mx28_rtc_regs *)MXS_RTC_BASE;
56 struct mx28_lcdif_regs *lcdif_regs =
57 (struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
60 * Shut down the LCD controller as it interferes with BootROM boot mode
63 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
65 /* Wait 1 uS before doing the actual watchdog reset */
66 writel(1, &rtc_regs->hw_rtc_watchdog);
67 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
69 /* Endless loop, reset will exit from here */
74 void enable_caches(void)
76 #ifndef CONFIG_SYS_ICACHE_OFF
79 #ifndef CONFIG_SYS_DCACHE_OFF
84 int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
87 if ((readl(®->reg) & mask) == mask)
95 int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
98 if ((readl(®->reg) & mask) == 0)
106 int mx28_reset_block(struct mxs_register_32 *reg)
109 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
111 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
115 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
118 writel(MX28_BLOCK_SFTRST, ®->reg_set);
120 /* Wait for CLKGATE being set */
121 if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
125 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
127 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
131 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
133 if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
139 void mx28_fixup_vt(uint32_t start_addr)
141 uint32_t *vt = (uint32_t *)0x20;
144 for (i = 0; i < 8; i++)
145 vt[i] = start_addr + (4 * i);
148 #ifdef CONFIG_ARCH_MISC_INIT
149 int arch_misc_init(void)
151 mx28_fixup_vt(gd->relocaddr);
156 int arch_cpu_init(void)
158 struct mx28_clkctrl_regs *clkctrl_regs =
159 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
160 extern uint32_t _start;
162 mx28_fixup_vt((uint32_t)&_start);
167 /* Clear bypass bit */
168 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
169 &clkctrl_regs->hw_clkctrl_clkseq_set);
171 /* Set GPMI clock to ref_gpmi / 12 */
172 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
173 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
178 * Configure GPIO unit
182 #ifdef CONFIG_APBH_DMA
190 #if defined(CONFIG_DISPLAY_CPUINFO)
191 static const char *get_cpu_type(void)
193 struct mx28_digctl_regs *digctl_regs =
194 (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
196 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
197 case HW_DIGCTL_CHIPID_MX28:
204 static const char *get_cpu_rev(void)
206 struct mx28_digctl_regs *digctl_regs =
207 (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
208 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
210 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
211 case HW_DIGCTL_CHIPID_MX28:
223 int print_cpuinfo(void)
225 struct mx28_spl_data *data = (struct mx28_spl_data *)
226 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
228 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
231 mxc_get_clock(MXC_ARM_CLK) / 1000000);
232 printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
237 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
239 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
240 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
241 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
242 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
247 * Initializes on-chip ethernet controllers.
249 #ifdef CONFIG_CMD_NET
250 int cpu_eth_init(bd_t *bis)
252 struct mx28_clkctrl_regs *clkctrl_regs =
253 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
255 /* Turn on ENET clocks */
256 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
257 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
259 /* Set up ENET PLL for 50 MHz */
260 /* Power on ENET PLL */
261 writel(CLKCTRL_PLL2CTRL0_POWER,
262 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
266 /* Gate on ENET PLL */
267 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
268 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
270 /* Enable pad output */
271 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
277 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
280 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
282 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
286 void mx28_adjust_mac(int dev_id, unsigned char *mac)
287 __attribute__((weak, alias("__mx28_adjust_mac")));
289 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
291 #define MXS_OCOTP_MAX_TIMEOUT 1000000
292 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
294 struct mx28_ocotp_regs *ocotp_regs =
295 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
300 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
302 if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
303 MXS_OCOTP_MAX_TIMEOUT)) {
304 printf("MXS FEC: Can't get MAC from OCOTP\n");
308 data = readl(&ocotp_regs->hw_ocotp_cust0);
310 mac[2] = (data >> 24) & 0xff;
311 mac[3] = (data >> 16) & 0xff;
312 mac[4] = (data >> 8) & 0xff;
313 mac[5] = data & 0xff;
314 mx28_adjust_mac(dev_id, mac);
317 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
323 int mx28_dram_init(void)
325 struct mx28_spl_data *data = (struct mx28_spl_data *)
326 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
328 if (data->mem_dram_size == 0) {
330 "Error, the RAM size passed up from SPL is 0!\n");
334 gd->ram_size = data->mem_dram_size;
339 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,