2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * Change to support call back into iMX28 bootrom
16 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
17 * on behalf of DENX Software Engineering GmbH
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm-offsets.h>
44 *************************************************************************
46 * Jump vector table as in table 3.1 in [1]
48 *************************************************************************
55 b undefined_instruction
64 * Vector table, located at address 0x20.
65 * This table allows the code running AFTER SPL, the U-Boot, to install it's
66 * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
67 * including it's interrupt vectoring table and the table at 0x0 is still the
68 * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
73 _vt_undefined_instruction:
75 _vt_software_interrupt:
90 undefined_instruction:
91 ldr pc, _vt_undefined_instruction
93 ldr pc, _vt_software_interrupt
95 ldr pc, _vt_prefetch_abort
97 ldr pc, _vt_data_abort
105 .balignl 16,0xdeadbeef
108 *************************************************************************
110 * Startup Code (reset vector)
112 * do important init only if we don't start from memory!
113 * setup Memory and board specific bits prior to relocation.
114 * relocate armboot to ram
117 *************************************************************************
122 .word CONFIG_SYS_TEXT_BASE
125 * These are defined in the board-specific linker script.
126 * Subtracting _start from them lets the linker put their
127 * relative position in the executable instead of leaving
130 .globl _bss_start_ofs
132 .word __bss_start - _start
136 .word __bss_end__ - _start
142 #ifdef CONFIG_USE_IRQ
143 /* IRQ stack memory (calculated at run-time) */
144 .globl IRQ_STACK_START
148 /* IRQ stack memory (calculated at run-time) */
149 .globl FIQ_STACK_START
154 /* IRQ stack memory (calculated at run-time) + 8 bytes */
155 .globl IRQ_STACK_START_IN
160 * the actual reset code
165 * Store all registers on old stack pointer, this will allow us later to
166 * return to the BootROM and let the BootROM load U-Boot into RAM.
171 * set the cpu to SVC32 mode
179 * we do sys-critical inits only at reboot,
180 * not when booting from ram!
182 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
192 *************************************************************************
194 * CPU_init_critical registers
196 * setup important registers
197 * setup memory timing
199 *************************************************************************
201 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
204 * flush v4 I/D caches
207 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
208 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
211 * disable MMU stuff and caches
213 mrc p15, 0, r0, c1, c0, 0
214 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
215 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
216 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
217 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
218 mcr p15, 0, r0, c1, c0, 0
220 mov pc, lr /* back to my caller */
223 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
226 ldr sp, _TEXT_BASE /* switch to abort stack */
228 bl 1b /* hang and never return */