2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
31 #include "mx28_init.h"
33 void mx28_power_clock2xtal(void)
35 struct mx28_clkctrl_regs *clkctrl_regs =
36 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
38 /* Set XTAL as CPU reference clock */
39 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
40 &clkctrl_regs->hw_clkctrl_clkseq_set);
43 void mx28_power_clock2pll(void)
45 struct mx28_clkctrl_regs *clkctrl_regs =
46 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
48 writel(CLKCTRL_PLL0CTRL0_POWER,
49 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
51 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
52 &clkctrl_regs->hw_clkctrl_clkseq_clr);
55 void mx28_power_clear_auto_restart(void)
57 struct mx28_rtc_regs *rtc_regs =
58 (struct mx28_rtc_regs *)MXS_RTC_BASE;
60 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
61 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
64 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
65 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
69 * Due to the hardware design bug of mx28 EVK-A
70 * we need to set the AUTO_RESTART bit.
72 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
75 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
78 setbits_le32(&rtc_regs->hw_rtc_persistent0,
79 RTC_PERSISTENT0_AUTO_RESTART);
80 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
81 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
82 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
88 void mx28_power_set_linreg(void)
90 struct mx28_power_regs *power_regs =
91 (struct mx28_power_regs *)MXS_POWER_BASE;
93 /* Set linear regulator 25mV below switching converter */
94 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
95 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
96 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
98 clrsetbits_le32(&power_regs->hw_power_vddactrl,
99 POWER_VDDACTRL_LINREG_OFFSET_MASK,
100 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
102 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
103 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
104 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
107 int mx28_get_batt_volt(void)
109 struct mx28_power_regs *power_regs =
110 (struct mx28_power_regs *)MXS_POWER_BASE;
111 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
112 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
113 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
118 int mx28_is_batt_ready(void)
120 return (mx28_get_batt_volt() >= 3600);
123 int mx28_is_batt_good(void)
125 struct mx28_power_regs *power_regs =
126 (struct mx28_power_regs *)MXS_POWER_BASE;
127 uint32_t volt = mx28_get_batt_volt();
129 if ((volt >= 2400) && (volt <= 4300))
132 clrsetbits_le32(&power_regs->hw_power_5vctrl,
133 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
134 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
135 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
136 &power_regs->hw_power_5vctrl_clr);
138 clrsetbits_le32(&power_regs->hw_power_charge,
139 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
140 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
142 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
143 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
144 &power_regs->hw_power_5vctrl_clr);
148 volt = mx28_get_batt_volt();
156 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
157 &power_regs->hw_power_charge_clr);
158 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
163 void mx28_power_setup_5v_detect(void)
165 struct mx28_power_regs *power_regs =
166 (struct mx28_power_regs *)MXS_POWER_BASE;
168 /* Start 5V detection */
169 clrsetbits_le32(&power_regs->hw_power_5vctrl,
170 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
171 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
172 POWER_5VCTRL_PWRUP_VBUS_CMPS);
175 void mx28_src_power_init(void)
177 struct mx28_power_regs *power_regs =
178 (struct mx28_power_regs *)MXS_POWER_BASE;
180 /* Improve efficieny and reduce transient ripple */
181 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
182 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
184 clrsetbits_le32(&power_regs->hw_power_dclimits,
185 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
186 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
188 setbits_le32(&power_regs->hw_power_battmonitor,
189 POWER_BATTMONITOR_EN_BATADJ);
191 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
192 clrsetbits_le32(&power_regs->hw_power_loopctrl,
193 POWER_LOOPCTRL_EN_RCSCALE_MASK,
194 POWER_LOOPCTRL_RCSCALE_THRESH |
195 POWER_LOOPCTRL_EN_RCSCALE_8X);
197 clrsetbits_le32(&power_regs->hw_power_minpwr,
198 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
200 /* 5V to battery handoff ... FIXME */
201 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
203 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
206 void mx28_power_init_4p2_params(void)
208 struct mx28_power_regs *power_regs =
209 (struct mx28_power_regs *)MXS_POWER_BASE;
211 /* Setup 4P2 parameters */
212 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
213 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
214 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
216 clrsetbits_le32(&power_regs->hw_power_5vctrl,
217 POWER_5VCTRL_HEADROOM_ADJ_MASK,
218 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
220 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
221 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
222 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
223 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
225 clrsetbits_le32(&power_regs->hw_power_5vctrl,
226 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
227 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
230 void mx28_enable_4p2_dcdc_input(int xfer)
232 struct mx28_power_regs *power_regs =
233 (struct mx28_power_regs *)MXS_POWER_BASE;
234 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
235 uint32_t prev_5v_brnout, prev_5v_droop;
237 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
238 POWER_5VCTRL_PWDN_5VBRNOUT;
239 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
240 POWER_CTRL_ENIRQ_VDD5V_DROOP;
242 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
243 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
244 &power_regs->hw_power_reset);
246 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
248 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
249 POWER_5VCTRL_ENABLE_DCDC)) {
254 * Recording orignal values that will be modified temporarlily
255 * to handle a chip bug. See chip errata for CQ ENGR00115837
257 tmp = readl(&power_regs->hw_power_5vctrl);
258 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
259 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
261 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
264 * Disable mechanisms that get erroneously tripped by when setting
265 * the DCDC4P2 EN_DCDC
267 clrbits_le32(&power_regs->hw_power_5vctrl,
268 POWER_5VCTRL_VBUSVALID_5VDETECT |
269 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
271 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
274 setbits_le32(&power_regs->hw_power_5vctrl,
275 POWER_5VCTRL_DCDC_XFER);
277 clrbits_le32(&power_regs->hw_power_5vctrl,
278 POWER_5VCTRL_DCDC_XFER);
280 setbits_le32(&power_regs->hw_power_5vctrl,
281 POWER_5VCTRL_ENABLE_DCDC);
283 setbits_le32(&power_regs->hw_power_dcdc4p2,
284 POWER_DCDC4P2_ENABLE_DCDC);
289 clrsetbits_le32(&power_regs->hw_power_5vctrl,
290 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
293 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
296 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
298 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
299 writel(POWER_CTRL_VBUS_VALID_IRQ,
300 &power_regs->hw_power_ctrl_clr);
302 if (prev_5v_brnout) {
303 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
304 &power_regs->hw_power_5vctrl_set);
305 writel(POWER_RESET_UNLOCK_KEY,
306 &power_regs->hw_power_reset);
308 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
309 &power_regs->hw_power_5vctrl_clr);
310 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
311 &power_regs->hw_power_reset);
314 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
315 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
316 &power_regs->hw_power_ctrl_clr);
319 clrbits_le32(&power_regs->hw_power_ctrl,
320 POWER_CTRL_ENIRQ_VDD5V_DROOP);
322 setbits_le32(&power_regs->hw_power_ctrl,
323 POWER_CTRL_ENIRQ_VDD5V_DROOP);
326 void mx28_power_init_4p2_regulator(void)
328 struct mx28_power_regs *power_regs =
329 (struct mx28_power_regs *)MXS_POWER_BASE;
332 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
334 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
336 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
337 &power_regs->hw_power_5vctrl_clr);
338 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
340 /* Power up the 4p2 rail and logic/control */
341 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
342 &power_regs->hw_power_5vctrl_clr);
345 * Start charging up the 4p2 capacitor. We ramp of this charge
346 * gradually to avoid large inrush current from the 5V cable which can
347 * cause transients/problems
349 mx28_enable_4p2_dcdc_input(0);
351 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
353 * If we arrived here, we were unable to recover from mx23 chip
354 * errata 5837. 4P2 is disabled and sufficient battery power is
355 * not present. Exiting to not enable DCDC power during 5V
358 clrbits_le32(&power_regs->hw_power_dcdc4p2,
359 POWER_DCDC4P2_ENABLE_DCDC);
360 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
361 &power_regs->hw_power_5vctrl_set);
366 * Here we set the 4p2 brownout level to something very close to 4.2V.
367 * We then check the brownout status. If the brownout status is false,
368 * the voltage is already close to the target voltage of 4.2V so we
369 * can go ahead and set the 4P2 current limit to our max target limit.
370 * If the brownout status is true, we need to ramp us the current limit
371 * so that we don't cause large inrush current issues. We step up the
372 * current limit until the brownout status is false or until we've
373 * reached our maximum defined 4p2 current limit.
375 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
376 POWER_DCDC4P2_BO_MASK,
377 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
379 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
380 setbits_le32(&power_regs->hw_power_5vctrl,
381 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
383 tmp = (readl(&power_regs->hw_power_5vctrl) &
384 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
385 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
387 if (!(readl(&power_regs->hw_power_sts) &
388 POWER_STS_DCDC_4P2_BO)) {
389 tmp = readl(&power_regs->hw_power_5vctrl);
390 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
392 writel(tmp, &power_regs->hw_power_5vctrl);
396 tmp2 = readl(&power_regs->hw_power_5vctrl);
397 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
399 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
400 writel(tmp2, &power_regs->hw_power_5vctrl);
406 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
407 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
410 void mx28_power_init_dcdc_4p2_source(void)
412 struct mx28_power_regs *power_regs =
413 (struct mx28_power_regs *)MXS_POWER_BASE;
415 if (!(readl(&power_regs->hw_power_dcdc4p2) &
416 POWER_DCDC4P2_ENABLE_DCDC)) {
420 mx28_enable_4p2_dcdc_input(1);
422 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
423 clrbits_le32(&power_regs->hw_power_dcdc4p2,
424 POWER_DCDC4P2_ENABLE_DCDC);
425 writel(POWER_5VCTRL_ENABLE_DCDC,
426 &power_regs->hw_power_5vctrl_clr);
427 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
428 &power_regs->hw_power_5vctrl_set);
432 void mx28_power_enable_4p2(void)
434 struct mx28_power_regs *power_regs =
435 (struct mx28_power_regs *)MXS_POWER_BASE;
436 uint32_t vdddctrl, vddactrl, vddioctrl;
439 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
440 vddactrl = readl(&power_regs->hw_power_vddactrl);
441 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
443 setbits_le32(&power_regs->hw_power_vdddctrl,
444 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
445 POWER_VDDDCTRL_PWDN_BRNOUT);
447 setbits_le32(&power_regs->hw_power_vddactrl,
448 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
449 POWER_VDDACTRL_PWDN_BRNOUT);
451 setbits_le32(&power_regs->hw_power_vddioctrl,
452 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
454 mx28_power_init_4p2_params();
455 mx28_power_init_4p2_regulator();
457 /* Shutdown battery (none present) */
458 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
459 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
460 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
462 mx28_power_init_dcdc_4p2_source();
464 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
466 writel(vddactrl, &power_regs->hw_power_vddactrl);
468 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
471 * Check if FET is enabled on either powerout and if so,
475 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
476 POWER_VDDDCTRL_DISABLE_FET);
477 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
478 POWER_VDDACTRL_DISABLE_FET);
479 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
480 POWER_VDDIOCTRL_DISABLE_FET);
482 writel(POWER_CHARGE_ENABLE_LOAD,
483 &power_regs->hw_power_charge_clr);
486 void mx28_boot_valid_5v(void)
488 struct mx28_power_regs *power_regs =
489 (struct mx28_power_regs *)MXS_POWER_BASE;
492 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
493 * disconnect event. FIXME
495 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
496 &power_regs->hw_power_5vctrl_set);
498 /* Configure polarity to check for 5V disconnection. */
499 writel(POWER_CTRL_POLARITY_VBUSVALID |
500 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
501 &power_regs->hw_power_ctrl_clr);
503 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
504 &power_regs->hw_power_ctrl_clr);
506 mx28_power_enable_4p2();
509 void mx28_powerdown(void)
511 struct mx28_power_regs *power_regs =
512 (struct mx28_power_regs *)MXS_POWER_BASE;
513 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
514 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
515 &power_regs->hw_power_reset);
518 void mx28_handle_5v_conflict(void)
520 struct mx28_power_regs *power_regs =
521 (struct mx28_power_regs *)MXS_POWER_BASE;
524 setbits_le32(&power_regs->hw_power_vddioctrl,
525 POWER_VDDIOCTRL_BO_OFFSET_MASK);
528 tmp = readl(&power_regs->hw_power_sts);
530 if (tmp & POWER_STS_VDDIO_BO) {
535 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
536 mx28_boot_valid_5v();
545 void mx28_5v_boot(void)
547 struct mx28_power_regs *power_regs =
548 (struct mx28_power_regs *)MXS_POWER_BASE;
551 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
552 * but their implementation always returns 1 so we omit it here.
554 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
555 mx28_boot_valid_5v();
560 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
561 mx28_boot_valid_5v();
565 mx28_handle_5v_conflict();
568 void mx28_init_batt_bo(void)
570 struct mx28_power_regs *power_regs =
571 (struct mx28_power_regs *)MXS_POWER_BASE;
574 clrsetbits_le32(&power_regs->hw_power_battmonitor,
575 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
576 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
578 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
579 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
582 void mx28_switch_vddd_to_dcdc_source(void)
584 struct mx28_power_regs *power_regs =
585 (struct mx28_power_regs *)MXS_POWER_BASE;
587 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
588 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
589 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
591 clrbits_le32(&power_regs->hw_power_vdddctrl,
592 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
593 POWER_VDDDCTRL_DISABLE_STEPPING);
596 void mx28_power_configure_power_source(void)
598 mx28_src_power_init();
601 mx28_power_clock2pll();
604 mx28_switch_vddd_to_dcdc_source();
607 void mx28_enable_output_rail_protection(void)
609 struct mx28_power_regs *power_regs =
610 (struct mx28_power_regs *)MXS_POWER_BASE;
612 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
613 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
615 setbits_le32(&power_regs->hw_power_vdddctrl,
616 POWER_VDDDCTRL_PWDN_BRNOUT);
618 setbits_le32(&power_regs->hw_power_vddactrl,
619 POWER_VDDACTRL_PWDN_BRNOUT);
621 setbits_le32(&power_regs->hw_power_vddioctrl,
622 POWER_VDDIOCTRL_PWDN_BRNOUT);
625 int mx28_get_vddio_power_source_off(void)
627 struct mx28_power_regs *power_regs =
628 (struct mx28_power_regs *)MXS_POWER_BASE;
631 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
632 tmp = readl(&power_regs->hw_power_vddioctrl);
633 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
634 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
635 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
640 if (!(readl(&power_regs->hw_power_5vctrl) &
641 POWER_5VCTRL_ENABLE_DCDC)) {
642 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
643 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
653 int mx28_get_vddd_power_source_off(void)
655 struct mx28_power_regs *power_regs =
656 (struct mx28_power_regs *)MXS_POWER_BASE;
659 tmp = readl(&power_regs->hw_power_vdddctrl);
660 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
661 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
662 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
667 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
668 if (!(readl(&power_regs->hw_power_5vctrl) &
669 POWER_5VCTRL_ENABLE_DCDC)) {
674 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
675 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
676 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
684 void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
686 struct mx28_power_regs *power_regs =
687 (struct mx28_power_regs *)MXS_POWER_BASE;
688 uint32_t cur_target, diff, bo_int = 0;
689 uint32_t powered_by_linreg = 0;
691 new_brownout = new_target - new_brownout;
693 cur_target = readl(&power_regs->hw_power_vddioctrl);
694 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
695 cur_target *= 50; /* 50 mV step*/
696 cur_target += 2800; /* 2800 mV lowest */
698 powered_by_linreg = mx28_get_vddio_power_source_off();
699 if (new_target > cur_target) {
701 if (powered_by_linreg) {
702 bo_int = readl(&power_regs->hw_power_vddioctrl);
703 clrbits_le32(&power_regs->hw_power_vddioctrl,
704 POWER_CTRL_ENIRQ_VDDIO_BO);
707 setbits_le32(&power_regs->hw_power_vddioctrl,
708 POWER_VDDIOCTRL_BO_OFFSET_MASK);
710 if (new_target - cur_target > 100)
711 diff = cur_target + 100;
718 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
719 POWER_VDDIOCTRL_TRG_MASK, diff);
721 if (powered_by_linreg ||
722 (readl(&power_regs->hw_power_sts) &
723 POWER_STS_VDD5V_GT_VDDIO))
726 while (!(readl(&power_regs->hw_power_sts) &
732 cur_target = readl(&power_regs->hw_power_vddioctrl);
733 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
734 cur_target *= 50; /* 50 mV step*/
735 cur_target += 2800; /* 2800 mV lowest */
736 } while (new_target > cur_target);
738 if (powered_by_linreg) {
739 writel(POWER_CTRL_VDDIO_BO_IRQ,
740 &power_regs->hw_power_ctrl_clr);
741 if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
742 setbits_le32(&power_regs->hw_power_vddioctrl,
743 POWER_CTRL_ENIRQ_VDDIO_BO);
747 if (cur_target - new_target > 100)
748 diff = cur_target - 100;
755 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
756 POWER_VDDIOCTRL_TRG_MASK, diff);
758 if (powered_by_linreg ||
759 (readl(&power_regs->hw_power_sts) &
760 POWER_STS_VDD5V_GT_VDDIO))
763 while (!(readl(&power_regs->hw_power_sts) &
769 cur_target = readl(&power_regs->hw_power_vddioctrl);
770 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
771 cur_target *= 50; /* 50 mV step*/
772 cur_target += 2800; /* 2800 mV lowest */
773 } while (new_target < cur_target);
776 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
777 POWER_VDDDCTRL_BO_OFFSET_MASK,
778 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
781 void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
783 struct mx28_power_regs *power_regs =
784 (struct mx28_power_regs *)MXS_POWER_BASE;
785 uint32_t cur_target, diff, bo_int = 0;
786 uint32_t powered_by_linreg = 0;
788 new_brownout = new_target - new_brownout;
790 cur_target = readl(&power_regs->hw_power_vdddctrl);
791 cur_target &= POWER_VDDDCTRL_TRG_MASK;
792 cur_target *= 25; /* 25 mV step*/
793 cur_target += 800; /* 800 mV lowest */
795 powered_by_linreg = mx28_get_vddd_power_source_off();
796 if (new_target > cur_target) {
797 if (powered_by_linreg) {
798 bo_int = readl(&power_regs->hw_power_vdddctrl);
799 clrbits_le32(&power_regs->hw_power_vdddctrl,
800 POWER_CTRL_ENIRQ_VDDD_BO);
803 setbits_le32(&power_regs->hw_power_vdddctrl,
804 POWER_VDDDCTRL_BO_OFFSET_MASK);
807 if (new_target - cur_target > 100)
808 diff = cur_target + 100;
815 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
816 POWER_VDDDCTRL_TRG_MASK, diff);
818 if (powered_by_linreg ||
819 (readl(&power_regs->hw_power_sts) &
820 POWER_STS_VDD5V_GT_VDDIO))
823 while (!(readl(&power_regs->hw_power_sts) &
829 cur_target = readl(&power_regs->hw_power_vdddctrl);
830 cur_target &= POWER_VDDDCTRL_TRG_MASK;
831 cur_target *= 25; /* 25 mV step*/
832 cur_target += 800; /* 800 mV lowest */
833 } while (new_target > cur_target);
835 if (powered_by_linreg) {
836 writel(POWER_CTRL_VDDD_BO_IRQ,
837 &power_regs->hw_power_ctrl_clr);
838 if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
839 setbits_le32(&power_regs->hw_power_vdddctrl,
840 POWER_CTRL_ENIRQ_VDDD_BO);
844 if (cur_target - new_target > 100)
845 diff = cur_target - 100;
852 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
853 POWER_VDDDCTRL_TRG_MASK, diff);
855 if (powered_by_linreg ||
856 (readl(&power_regs->hw_power_sts) &
857 POWER_STS_VDD5V_GT_VDDIO))
860 while (!(readl(&power_regs->hw_power_sts) &
866 cur_target = readl(&power_regs->hw_power_vdddctrl);
867 cur_target &= POWER_VDDDCTRL_TRG_MASK;
868 cur_target *= 25; /* 25 mV step*/
869 cur_target += 800; /* 800 mV lowest */
870 } while (new_target < cur_target);
873 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
874 POWER_VDDDCTRL_BO_OFFSET_MASK,
875 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
878 void mx28_setup_batt_detect(void)
881 mx28_lradc_enable_batt_measurement();
885 void mx28_power_init(void)
887 struct mx28_power_regs *power_regs =
888 (struct mx28_power_regs *)MXS_POWER_BASE;
890 mx28_power_clock2xtal();
891 mx28_power_clear_auto_restart();
892 mx28_power_set_linreg();
893 mx28_power_setup_5v_detect();
895 mx28_setup_batt_detect();
897 mx28_power_configure_power_source();
898 mx28_enable_output_rail_protection();
900 mx28_power_set_vddio(3300, 3150);
902 mx28_power_set_vddd(1350, 1200);
904 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
905 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
906 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
907 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
909 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
914 #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
915 void mx28_power_wait_pswitch(void)
917 struct mx28_power_regs *power_regs =
918 (struct mx28_power_regs *)MXS_POWER_BASE;
920 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))