2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/iomux.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/sys_proto.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 /* 1 second delay should be plenty of time for block reset. */
41 #define RESET_MAX_TIMEOUT 1000000
43 #define MX28_BLOCK_SFTRST (1 << 31)
44 #define MX28_BLOCK_CLKGATE (1 << 30)
46 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
47 inline void lowlevel_init(void) {}
49 void reset_cpu(ulong ignored) __attribute__((noreturn));
51 void reset_cpu(ulong ignored)
54 struct mx28_rtc_regs *rtc_regs =
55 (struct mx28_rtc_regs *)MXS_RTC_BASE;
57 /* Wait 1 uS before doing the actual watchdog reset */
58 writel(1, &rtc_regs->hw_rtc_watchdog);
59 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
61 /* Endless loop, reset will exit from here */
66 int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
69 if ((readl(®->reg) & mask) == mask)
77 int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
80 if ((readl(®->reg) & mask) == 0)
88 int mx28_reset_block(struct mx28_register *reg)
91 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
93 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
97 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
100 writel(MX28_BLOCK_SFTRST, ®->reg_set);
102 /* Wait for CLKGATE being set */
103 if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
107 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
109 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
113 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
115 if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
121 void mx28_fixup_vt(uint32_t start_addr)
123 uint32_t *vt = (uint32_t *)0x20;
126 for (i = 0; i < 8; i++)
127 vt[i] = start_addr + (4 * i);
130 #ifdef CONFIG_ARCH_MISC_INIT
131 int arch_misc_init(void)
133 mx28_fixup_vt(gd->relocaddr);
138 #ifdef CONFIG_ARCH_CPU_INIT
139 int arch_cpu_init(void)
141 struct mx28_clkctrl_regs *clkctrl_regs =
142 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
143 extern uint32_t _start;
145 mx28_fixup_vt((uint32_t)&_start);
150 /* Clear bypass bit */
151 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
152 &clkctrl_regs->hw_clkctrl_clkseq_set);
154 /* Set GPMI clock to ref_gpmi / 12 */
155 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
156 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
161 * Configure GPIO unit
169 #if defined(CONFIG_DISPLAY_CPUINFO)
170 int print_cpuinfo(void)
172 printf("Freescale i.MX28 family\n");
177 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
179 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
180 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
181 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
182 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
187 * Initializes on-chip ethernet controllers.
189 #ifdef CONFIG_CMD_NET
190 int cpu_eth_init(bd_t *bis)
192 struct mx28_clkctrl_regs *clkctrl_regs =
193 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
195 /* Turn on ENET clocks */
196 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
197 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
199 /* Set up ENET PLL for 50 MHz */
200 /* Power on ENET PLL */
201 writel(CLKCTRL_PLL2CTRL0_POWER,
202 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
206 /* Gate on ENET PLL */
207 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
208 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
210 /* Enable pad output */
211 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
217 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
220 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
222 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
226 void mx28_adjust_mac(int dev_id, unsigned char *mac)
227 __attribute__((weak, alias("__mx28_adjust_mac")));
229 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
231 #define MXS_OCOTP_MAX_TIMEOUT 1000000
232 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
234 struct mx28_ocotp_regs *ocotp_regs =
235 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
240 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
242 if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
243 MXS_OCOTP_MAX_TIMEOUT)) {
244 printf("MXS FEC: Can't get MAC from OCOTP\n");
248 data = readl(&ocotp_regs->hw_ocotp_cust0);
250 mac[2] = (data >> 24) & 0xff;
251 mac[3] = (data >> 16) & 0xff;
252 mac[4] = (data >> 8) & 0xff;
253 mac[5] = data & 0xff;
254 mx28_adjust_mac(dev_id, mac);
257 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
264 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,