2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 /* 1 second delay should be plenty of time for block reset. */
42 #define RESET_MAX_TIMEOUT 1000000
44 #define MX28_BLOCK_SFTRST (1 << 31)
45 #define MX28_BLOCK_CLKGATE (1 << 30)
47 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
48 inline void lowlevel_init(void) {}
50 void reset_cpu(ulong ignored) __attribute__((noreturn));
52 void reset_cpu(ulong ignored)
55 struct mx28_rtc_regs *rtc_regs =
56 (struct mx28_rtc_regs *)MXS_RTC_BASE;
58 /* Wait 1 uS before doing the actual watchdog reset */
59 writel(1, &rtc_regs->hw_rtc_watchdog);
60 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
62 /* Endless loop, reset will exit from here */
67 void enable_caches(void)
69 #ifndef CONFIG_SYS_ICACHE_OFF
72 #ifndef CONFIG_SYS_DCACHE_OFF
77 int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
80 if ((readl(®->reg) & mask) == mask)
88 int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
91 if ((readl(®->reg) & mask) == 0)
99 int mx28_reset_block(struct mx28_register_32 *reg)
102 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
104 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
108 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
111 writel(MX28_BLOCK_SFTRST, ®->reg_set);
113 /* Wait for CLKGATE being set */
114 if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
118 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
120 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
124 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
126 if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
132 void mx28_fixup_vt(uint32_t start_addr)
134 uint32_t *vt = (uint32_t *)0x20;
137 for (i = 0; i < 8; i++)
138 vt[i] = start_addr + (4 * i);
141 #ifdef CONFIG_ARCH_MISC_INIT
142 int arch_misc_init(void)
144 mx28_fixup_vt(gd->relocaddr);
149 #ifdef CONFIG_ARCH_CPU_INIT
150 int arch_cpu_init(void)
152 struct mx28_clkctrl_regs *clkctrl_regs =
153 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
154 extern uint32_t _start;
156 mx28_fixup_vt((uint32_t)&_start);
161 /* Clear bypass bit */
162 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
163 &clkctrl_regs->hw_clkctrl_clkseq_set);
165 /* Set GPMI clock to ref_gpmi / 12 */
166 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
167 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
172 * Configure GPIO unit
176 #ifdef CONFIG_APBH_DMA
185 #if defined(CONFIG_DISPLAY_CPUINFO)
186 int print_cpuinfo(void)
188 printf("Freescale i.MX28 family at %d MHz\n",
189 mxc_get_clock(MXC_ARM_CLK) / 1000000);
194 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
196 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
197 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
198 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
199 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
204 * Initializes on-chip ethernet controllers.
206 #ifdef CONFIG_CMD_NET
207 int cpu_eth_init(bd_t *bis)
209 struct mx28_clkctrl_regs *clkctrl_regs =
210 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
212 /* Turn on ENET clocks */
213 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
214 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
216 /* Set up ENET PLL for 50 MHz */
217 /* Power on ENET PLL */
218 writel(CLKCTRL_PLL2CTRL0_POWER,
219 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
223 /* Gate on ENET PLL */
224 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
225 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
227 /* Enable pad output */
228 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
234 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
237 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
239 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
243 void mx28_adjust_mac(int dev_id, unsigned char *mac)
244 __attribute__((weak, alias("__mx28_adjust_mac")));
246 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
248 #define MXS_OCOTP_MAX_TIMEOUT 1000000
249 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
251 struct mx28_ocotp_regs *ocotp_regs =
252 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
257 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
259 if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
260 MXS_OCOTP_MAX_TIMEOUT)) {
261 printf("MXS FEC: Can't get MAC from OCOTP\n");
265 data = readl(&ocotp_regs->hw_ocotp_cust0);
267 mac[2] = (data >> 24) & 0xff;
268 mac[3] = (data >> 16) & 0xff;
269 mac[4] = (data >> 8) & 0xff;
270 mac[5] = data & 0xff;
271 mx28_adjust_mac(dev_id, mac);
274 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
280 int mx28_dram_init(void)
282 struct mx28_spl_data *data = (struct mx28_spl_data *)
283 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
285 if (data->mem_dram_size == 0) {
287 "Error, the RAM size passed up from SPL is 0!\n");
291 gd->ram_size = data->mem_dram_size;
296 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,