2 * Freescale i.MX28 clock setup code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/imx-regs.h>
35 /* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
36 #define PLL_FREQ_KHZ 480000
37 #define PLL_FREQ_COEF 18
38 /* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
39 #define XTAL_FREQ_KHZ 24000
41 #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
42 #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
44 static uint32_t mx28_get_pclk(void)
46 struct mx28_clkctrl_regs *clkctrl_regs =
47 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
49 uint32_t clkctrl, clkseq, clkfrac;
52 clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
54 /* No support of fractional divider calculation */
56 (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
60 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
63 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
64 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
65 CLKCTRL_CPU_DIV_XTAL_OFFSET;
66 return XTAL_FREQ_MHZ / div;
70 clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
71 frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
72 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
73 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
76 static uint32_t mx28_get_hclk(void)
78 struct mx28_clkctrl_regs *clkctrl_regs =
79 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
84 clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
86 /* No support of fractional divider calculation */
87 if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
90 div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
91 return mx28_get_pclk() / div;
94 static uint32_t mx28_get_emiclk(void)
96 struct mx28_clkctrl_regs *clkctrl_regs =
97 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
100 uint32_t clkctrl, clkseq, clkfrac;
102 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
103 clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
106 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
107 div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
108 CLKCTRL_EMI_DIV_XTAL_OFFSET;
109 return XTAL_FREQ_MHZ / div;
112 clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
115 frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
116 CLKCTRL_FRAC0_EMIFRAC_OFFSET;
117 div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
118 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
121 static uint32_t mx28_get_gpmiclk(void)
123 struct mx28_clkctrl_regs *clkctrl_regs =
124 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
127 uint32_t clkctrl, clkseq, clkfrac;
129 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
130 clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
133 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
134 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
135 return XTAL_FREQ_MHZ / div;
138 clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
141 frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
142 CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
143 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
144 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
148 * Set IO clock frequency, in kHz
150 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
152 struct mx28_clkctrl_regs *clkctrl_regs =
153 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
162 div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
170 if (io == MXC_IOCLK0) {
171 writel(CLKCTRL_FRAC0_CLKGATEIO0,
172 &clkctrl_regs->hw_clkctrl_frac0_set);
173 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
174 CLKCTRL_FRAC0_IO0FRAC_MASK,
175 div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
176 writel(CLKCTRL_FRAC0_CLKGATEIO0,
177 &clkctrl_regs->hw_clkctrl_frac0_clr);
179 writel(CLKCTRL_FRAC0_CLKGATEIO1,
180 &clkctrl_regs->hw_clkctrl_frac0_set);
181 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
182 CLKCTRL_FRAC0_IO1FRAC_MASK,
183 div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
184 writel(CLKCTRL_FRAC0_CLKGATEIO1,
185 &clkctrl_regs->hw_clkctrl_frac0_clr);
190 * Get IO clock, returns IO clock in kHz
192 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
194 struct mx28_clkctrl_regs *clkctrl_regs =
195 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
201 tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
203 if (io == MXC_IOCLK0)
204 ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
205 CLKCTRL_FRAC0_IO0FRAC_OFFSET;
207 ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
208 CLKCTRL_FRAC0_IO1FRAC_OFFSET;
210 return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
214 * Configure SSP clock frequency, in kHz
216 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
218 struct mx28_clkctrl_regs *clkctrl_regs =
219 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
220 uint32_t clk, clkreg;
222 if (ssp > MXC_SSPCLK3)
225 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
226 (ssp * sizeof(struct mx28_register_32));
228 clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
229 while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
235 clk = mx28_get_ioclk(ssp >> 1);
240 /* Calculate the divider and cap it if necessary */
242 if (clk > CLKCTRL_SSP_DIV_MASK)
243 clk = CLKCTRL_SSP_DIV_MASK;
245 clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
246 while (readl(clkreg) & CLKCTRL_SSP_BUSY)
250 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
251 &clkctrl_regs->hw_clkctrl_clkseq_set);
253 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
254 &clkctrl_regs->hw_clkctrl_clkseq_clr);
258 * Return SSP frequency, in kHz
260 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
262 struct mx28_clkctrl_regs *clkctrl_regs =
263 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
267 if (ssp > MXC_SSPCLK3)
270 tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
271 if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
272 return XTAL_FREQ_KHZ;
274 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
275 (ssp * sizeof(struct mx28_register_32));
277 tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
282 clk = mx28_get_ioclk(ssp >> 1);
288 * Set SSP/MMC bus frequency, in kHz)
290 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
292 struct mx28_ssp_regs *ssp_regs;
293 const uint32_t sspclk = mx28_get_sspclk(bus);
295 uint32_t divide, rate, tgtclk;
297 ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
300 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
301 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
302 * CLOCK_RATE could be any integer from 0 to 255.
304 for (divide = 2; divide < 254; divide += 2) {
305 rate = sspclk / freq / divide;
310 tgtclk = sspclk / divide / rate;
311 while (tgtclk > freq) {
313 tgtclk = sspclk / divide / rate;
318 /* Always set timeout the maximum */
319 reg = SSP_TIMING_TIMEOUT_MASK |
320 (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
321 ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
322 writel(reg, &ssp_regs->hw_ssp_timing);
324 debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
328 uint32_t mxc_get_clock(enum mxc_clock clk)
332 return mx28_get_pclk() * 1000000;
334 return mx28_get_gpmiclk() * 1000000;
337 return mx28_get_hclk() * 1000000;
339 return mx28_get_emiclk();
341 return mx28_get_ioclk(MXC_IOCLK0);
343 return mx28_get_ioclk(MXC_IOCLK1);
345 return mx28_get_sspclk(MXC_SSPCLK0);
347 return mx28_get_sspclk(MXC_SSPCLK1);
349 return mx28_get_sspclk(MXC_SSPCLK2);
351 return mx28_get_sspclk(MXC_SSPCLK3);