2 * Freescale i.MX28 clock setup code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/imx-regs.h>
35 /* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
36 #define PLL_FREQ_KHZ 480000
37 #define PLL_FREQ_COEF 18
38 /* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
39 #define XTAL_FREQ_KHZ 24000
41 #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
42 #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
44 static uint32_t mx28_get_pclk(void)
46 struct mx28_clkctrl_regs *clkctrl_regs =
47 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
49 uint32_t clkctrl, clkseq, div;
50 uint8_t clkfrac, frac;
52 clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
54 /* No support of fractional divider calculation */
56 (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
60 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
63 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
64 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
65 CLKCTRL_CPU_DIV_XTAL_OFFSET;
66 return XTAL_FREQ_MHZ / div;
70 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
71 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
72 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
73 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
76 static uint32_t mx28_get_hclk(void)
78 struct mx28_clkctrl_regs *clkctrl_regs =
79 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
84 clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
86 /* No support of fractional divider calculation */
87 if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
90 div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
91 return mx28_get_pclk() / div;
94 static uint32_t mx28_get_emiclk(void)
96 struct mx28_clkctrl_regs *clkctrl_regs =
97 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
99 uint32_t clkctrl, clkseq, div;
100 uint8_t clkfrac, frac;
102 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
103 clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
106 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
107 div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
108 CLKCTRL_EMI_DIV_XTAL_OFFSET;
109 return XTAL_FREQ_MHZ / div;
113 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
114 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
115 div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
116 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
119 static uint32_t mx28_get_gpmiclk(void)
121 struct mx28_clkctrl_regs *clkctrl_regs =
122 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
124 uint32_t clkctrl, clkseq, div;
125 uint8_t clkfrac, frac;
127 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
128 clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
131 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
132 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
133 return XTAL_FREQ_MHZ / div;
137 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
138 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
139 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
140 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
144 * Set IO clock frequency, in kHz
146 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
148 struct mx28_clkctrl_regs *clkctrl_regs =
149 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
156 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
159 div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
167 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
168 writeb(CLKCTRL_FRAC_CLKGATE,
169 &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
170 writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
171 &clkctrl_regs->hw_clkctrl_frac0[io_reg]);
172 writeb(CLKCTRL_FRAC_CLKGATE,
173 &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
177 * Get IO clock, returns IO clock in kHz
179 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
181 struct mx28_clkctrl_regs *clkctrl_regs =
182 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
186 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
189 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
191 ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
192 CLKCTRL_FRAC_FRAC_MASK;
194 return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
198 * Configure SSP clock frequency, in kHz
200 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
202 struct mx28_clkctrl_regs *clkctrl_regs =
203 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
204 uint32_t clk, clkreg;
206 if (ssp > MXC_SSPCLK3)
209 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
210 (ssp * sizeof(struct mx28_register_32));
212 clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
213 while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
219 clk = mx28_get_ioclk(ssp >> 1);
224 /* Calculate the divider and cap it if necessary */
226 if (clk > CLKCTRL_SSP_DIV_MASK)
227 clk = CLKCTRL_SSP_DIV_MASK;
229 clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
230 while (readl(clkreg) & CLKCTRL_SSP_BUSY)
234 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
235 &clkctrl_regs->hw_clkctrl_clkseq_set);
237 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
238 &clkctrl_regs->hw_clkctrl_clkseq_clr);
242 * Return SSP frequency, in kHz
244 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
246 struct mx28_clkctrl_regs *clkctrl_regs =
247 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
251 if (ssp > MXC_SSPCLK3)
254 tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
255 if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
256 return XTAL_FREQ_KHZ;
258 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
259 (ssp * sizeof(struct mx28_register_32));
261 tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
266 clk = mx28_get_ioclk(ssp >> 1);
272 * Set SSP/MMC bus frequency, in kHz)
274 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
276 struct mx28_ssp_regs *ssp_regs;
277 const uint32_t sspclk = mx28_get_sspclk(bus);
279 uint32_t divide, rate, tgtclk;
281 ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
284 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
285 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
286 * CLOCK_RATE could be any integer from 0 to 255.
288 for (divide = 2; divide < 254; divide += 2) {
289 rate = sspclk / freq / divide;
294 tgtclk = sspclk / divide / rate;
295 while (tgtclk > freq) {
297 tgtclk = sspclk / divide / rate;
302 /* Always set timeout the maximum */
303 reg = SSP_TIMING_TIMEOUT_MASK |
304 (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
305 ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
306 writel(reg, &ssp_regs->hw_ssp_timing);
308 debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
312 uint32_t mxc_get_clock(enum mxc_clock clk)
316 return mx28_get_pclk() * 1000000;
318 return mx28_get_gpmiclk() * 1000000;
321 return mx28_get_hclk() * 1000000;
323 return mx28_get_emiclk();
325 return mx28_get_ioclk(MXC_IOCLK0);
327 return mx28_get_ioclk(MXC_IOCLK1);
329 return mx28_get_sspclk(MXC_SSPCLK0);
331 return mx28_get_sspclk(MXC_SSPCLK1);
333 return mx28_get_sspclk(MXC_SSPCLK2);
335 return mx28_get_sspclk(MXC_SSPCLK3);