2 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
3 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/clock.h>
28 #include <asm/arch/mxcmmc.h>
32 * get the system pll clock in Hz
34 * mfi + mfn / (mfd +1)
35 * f = 2 * f_ref * --------------------
38 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
40 unsigned int mfi = (pll >> 10) & 0xf;
41 unsigned int mfn = pll & 0x3ff;
42 unsigned int mfd = (pll >> 16) & 0x3ff;
43 unsigned int pd = (pll >> 26) & 0xf;
45 mfi = mfi <= 5 ? 5 : mfi;
47 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
48 (mfd + 1) * (pd + 1));
51 static ulong clk_in_32k(void)
53 return 1024 * CONFIG_MX27_CLK32;
56 static ulong clk_in_26m(void)
58 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
60 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
62 return 26000000 * 2 / 3;
68 static ulong imx_get_mpllclk(void)
70 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
71 ulong cscr = readl(&pll->cscr);
74 if (cscr & CSCR_MCU_SEL)
79 return imx_decode_pll(readl(&pll->mpctl0), fref);
82 static ulong imx_get_armclk(void)
84 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
85 ulong cscr = readl(&pll->cscr);
86 ulong fref = imx_get_mpllclk();
89 if (!(cscr & CSCR_ARM_SRC_MPLL))
90 fref = lldiv((fref * 2), 3);
92 div = ((cscr >> 12) & 0x3) + 1;
94 return lldiv(fref, div);
97 static ulong imx_get_ahbclk(void)
99 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
100 ulong cscr = readl(&pll->cscr);
101 ulong fref = imx_get_mpllclk();
104 div = ((cscr >> 8) & 0x3) + 1;
106 return lldiv(fref * 2, 3 * div);
109 static __attribute__((unused)) ulong imx_get_spllclk(void)
111 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
112 ulong cscr = readl(&pll->cscr);
115 if (cscr & CSCR_SP_SEL)
120 return imx_decode_pll(readl(&pll->spctl0), fref);
123 static ulong imx_decode_perclk(ulong div)
125 return lldiv((imx_get_mpllclk() * 2), (div * 3));
128 static ulong imx_get_perclk1(void)
130 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
132 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
135 static ulong imx_get_perclk2(void)
137 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
139 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
142 static __attribute__((unused)) ulong imx_get_perclk3(void)
144 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
146 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
149 static __attribute__((unused)) ulong imx_get_perclk4(void)
151 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
153 return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
156 unsigned int mxc_get_clock(enum mxc_clock clk)
160 return imx_get_armclk();
162 return imx_get_perclk1();
164 return imx_get_ahbclk();
166 return imx_get_perclk2();
172 #if defined(CONFIG_DISPLAY_CPUINFO)
173 int print_cpuinfo (void)
177 printf("CPU: Freescale i.MX27 at %s MHz\n\n",
178 strmhz(buf, imx_get_mpllclk()));
183 int cpu_eth_init(bd_t *bis)
185 #if defined(CONFIG_FEC_MXC)
186 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
188 /* enable FEC clock */
189 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
190 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
191 return fecmxc_initialize(bis);
198 * Initializes on-chip MMC controllers.
199 * to override, implement board_mmc_init()
201 int cpu_mmc_init(bd_t *bis)
203 #ifdef CONFIG_MXC_MMC
204 return mxc_mmc_init(bis);
210 void imx_gpio_mode(int gpio_mode)
212 struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
213 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
214 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
215 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
216 unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
217 unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
221 if (gpio_mode & GPIO_PUEN) {
222 writel(readl(®s->port[port].puen) | (1 << pin),
223 ®s->port[port].puen);
225 writel(readl(®s->port[port].puen) & ~(1 << pin),
226 ®s->port[port].puen);
230 if (gpio_mode & GPIO_OUT) {
231 writel(readl(®s->port[port].ddir) | 1 << pin,
232 ®s->port[port].ddir);
234 writel(readl(®s->port[port].ddir) & ~(1 << pin),
235 ®s->port[port].ddir);
238 /* Primary / alternate function */
239 if (gpio_mode & GPIO_AF) {
240 writel(readl(®s->port[port].gpr) | (1 << pin),
241 ®s->port[port].gpr);
243 writel(readl(®s->port[port].gpr) & ~(1 << pin),
244 ®s->port[port].gpr);
248 if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
249 writel(readl(®s->port[port].gius) | (1 << pin),
250 ®s->port[port].gius);
252 writel(readl(®s->port[port].gius) & ~(1 << pin),
253 ®s->port[port].gius);
256 /* Output / input configuration */
258 tmp = readl(®s->port[port].ocr1);
259 tmp &= ~(3 << (pin * 2));
260 tmp |= (ocr << (pin * 2));
261 writel(tmp, ®s->port[port].ocr1);
263 writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
264 ®s->port[port].iconfa1);
265 writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
266 ®s->port[port].iconfa1);
267 writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
268 ®s->port[port].iconfb1);
269 writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
270 ®s->port[port].iconfb1);
274 tmp = readl(®s->port[port].ocr2);
275 tmp &= ~(3 << (pin * 2));
276 tmp |= (ocr << (pin * 2));
277 writel(tmp, ®s->port[port].ocr2);
279 writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
280 ®s->port[port].iconfa2);
281 writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
282 ®s->port[port].iconfa2);
283 writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
284 ®s->port[port].iconfb2);
285 writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
286 ®s->port[port].iconfb2);
290 #ifdef CONFIG_MXC_UART
291 void mx27_uart1_init_pins(void)
294 unsigned int mode[] = {
299 for (i = 0; i < ARRAY_SIZE(mode); i++)
300 imx_gpio_mode(mode[i]);
303 #endif /* CONFIG_MXC_UART */
305 #ifdef CONFIG_FEC_MXC
306 void mx27_fec_init_pins(void)
309 unsigned int mode[] = {
319 PD9_AIN_FEC_MDC | GPIO_PUEN,
321 PD11_AOUT_FEC_TX_CLK,
330 for (i = 0; i < ARRAY_SIZE(mode); i++)
331 imx_gpio_mode(mode[i]);
334 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
337 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
338 struct fuse_bank *bank = &iim->bank[0];
339 struct fuse_bank0_regs *fuse =
340 (struct fuse_bank0_regs *)bank->fuse_regs;
342 for (i = 0; i < 6; i++)
343 mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
345 #endif /* CONFIG_FEC_MXC */
347 #ifdef CONFIG_MXC_MMC
348 void mx27_sd1_init_pins(void)
351 unsigned int mode[] = {
360 for (i = 0; i < ARRAY_SIZE(mode); i++)
361 imx_gpio_mode(mode[i]);
365 void mx27_sd2_init_pins(void)
368 unsigned int mode[] = {
377 for (i = 0; i < ARRAY_SIZE(mode); i++)
378 imx_gpio_mode(mode[i]);
381 #endif /* CONFIG_MXC_MMC */