2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on mx27/generic.c:
6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
9 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-imx/cpu.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/clock.h>
20 #ifdef CONFIG_FSL_ESDHC
21 #include <fsl_esdhc.h>
23 DECLARE_GLOBAL_DATA_PTR;
27 * get the system pll clock in Hz
29 * mfi + mfn / (mfd +1)
30 * f = 2 * f_ref * --------------------
33 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
35 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
37 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
39 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
41 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
44 mfi = mfi <= 5 ? 5 : mfi;
45 mfn = mfn >= 512 ? mfn - 1024 : mfn;
49 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
53 static ulong imx_get_mpllclk(void)
55 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
56 ulong fref = MXC_HCLK;
58 return imx_decode_pll(readl(&ccm->mpctl), fref);
61 static ulong imx_get_upllclk(void)
63 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
64 ulong fref = MXC_HCLK;
66 return imx_decode_pll(readl(&ccm->upctl), fref);
69 static ulong imx_get_armclk(void)
71 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
72 ulong cctl = readl(&ccm->cctl);
73 ulong fref = imx_get_mpllclk();
76 if (cctl & CCM_CCTL_ARM_SRC)
77 fref = lldiv((u64) fref * 3, 4);
79 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
80 & CCM_CCTL_ARM_DIV_MASK) + 1;
85 static ulong imx_get_ahbclk(void)
87 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
88 ulong cctl = readl(&ccm->cctl);
89 ulong fref = imx_get_armclk();
92 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
93 & CCM_CCTL_AHB_DIV_MASK) + 1;
98 static ulong imx_get_ipgclk(void)
100 return imx_get_ahbclk() / 2;
103 static ulong imx_get_perclk(int clk)
105 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
106 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
110 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
111 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
116 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
118 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
119 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
120 ulong div = (fref + freq - 1) / freq;
122 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
125 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
126 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
127 div << CCM_PERCLK_SHIFT(clk));
129 setbits_le32(&ccm->mcr, 1 << clk);
131 clrbits_le32(&ccm->mcr, 1 << clk);
135 unsigned int mxc_get_clock(enum mxc_clock clk)
137 if (clk >= MXC_CLK_NUM)
141 return imx_get_armclk();
143 return imx_get_ahbclk();
147 return imx_get_ipgclk();
149 return imx_get_perclk(clk);
153 u32 get_cpu_rev(void)
156 u32 system_rev = 0x25000;
158 /* read SREV register from IIM module */
159 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
160 srev = readl(&iim->iim_srev);
164 system_rev |= CHIP_REV_1_0;
167 system_rev |= CHIP_REV_1_1;
170 system_rev |= CHIP_REV_1_2;
173 system_rev |= 0x8000;
180 #if defined(CONFIG_DISPLAY_CPUINFO)
181 static char *get_reset_cause(void)
183 /* read RCSR register from CCM module */
184 struct ccm_regs *ccm =
185 (struct ccm_regs *)IMX_CCM_BASE;
187 u32 cause = readl(&ccm->rcsr) & 0x0f;
193 else if ((cause & 2) == 2)
195 else if ((cause & 4) == 4)
197 else if ((cause & 8) == 8)
200 return "unknown reset";
204 int print_cpuinfo(void)
207 u32 cpurev = get_cpu_rev();
209 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
210 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
211 ((cpurev & 0x8000) ? " unknown" : ""),
212 strmhz(buf, imx_get_armclk()));
213 printf("Reset cause: %s\n", get_reset_cause());
218 void enable_caches(void)
220 #ifndef CONFIG_SYS_DCACHE_OFF
221 /* Enable D-cache. I-cache is already enabled in start.S */
226 #if defined(CONFIG_FEC_MXC)
228 * Initializes on-chip ethernet controllers.
229 * to override, implement board_eth_init()
231 int cpu_eth_init(bd_t *bis)
233 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
236 val = readl(&ccm->cgr0);
238 writel(val, &ccm->cgr0);
239 return fecmxc_initialize(bis);
245 #ifdef CONFIG_FSL_ESDHC
246 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
247 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
249 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
255 #ifdef CONFIG_FSL_ESDHC
257 * Initializes on-chip MMC controllers.
258 * to override, implement board_mmc_init()
260 int cpu_mmc_init(bd_t *bis)
262 return fsl_esdhc_mmc_init(bis);
266 #ifdef CONFIG_FEC_MXC
267 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
270 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
271 struct fuse_bank *bank = &iim->bank[0];
272 struct fuse_bank0_regs *fuse =
273 (struct fuse_bank0_regs *)bank->fuse_regs;
275 for (i = 0; i < 6; i++)
276 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
278 #endif /* CONFIG_FEC_MXC */