2 * SoC-specific lowlevel code for tms320dm365 and similar chips
3 * Actually used for booting from NAND with nand_spl.
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <asm/arch/dm365_lowlevel.h>
30 #include <asm/arch/hardware.h>
32 void dm365_waitloop(unsigned long loopcnt)
36 for (i = 0; i < loopcnt; i++)
40 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
42 unsigned int clksrc = 0x0;
44 /* Power up the PLL */
45 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
47 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
48 setbits_le32(&dv_pll0_regs->pllctl,
49 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
52 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
55 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
57 /* Set PLLEN=0 => PLL BYPASS MODE */
58 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
62 /* PLLRST=1(reset assert) */
63 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
67 /*Bring PLL out of Reset*/
68 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
70 /* Program the Multiper and Pre-Divider for PLL1 */
71 writel(pllmult, &dv_pll0_regs->pllm);
72 writel(prediv, &dv_pll0_regs->prediv);
74 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
75 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
76 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
77 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
78 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
79 &dv_pll0_regs->secctl);
80 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
81 writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
82 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
83 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
85 /* Program the PostDiv for PLL1 */
86 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
88 /* Post divider setting for PLL1 */
89 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
90 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
91 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
92 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
93 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
94 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
95 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
96 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
97 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
101 /* Set the GOSET bit */
102 writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
106 /* Wait for PLL to LOCK */
107 while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
111 /* Enable the PLL Bit of PLLCTL*/
112 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
117 int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
119 unsigned int clksrc = 0x0;
121 /* Power up the PLL*/
122 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
125 * Select the Clock Mode as Onchip Oscilator or External Clock on
127 * VDB has input on MXI pin
129 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
130 setbits_le32(&dv_pll1_regs->pllctl,
131 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
134 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
137 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
139 /* Set PLLEN=0 => PLL BYPASS MODE */
140 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
144 /* PLLRST=1(reset assert) */
145 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
149 /* Bring PLL out of Reset */
150 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
152 /* Program the Multiper and Pre-Divider for PLL2 */
153 writel(pllm, &dv_pll1_regs->pllm);
154 writel(prediv, &dv_pll1_regs->prediv);
156 writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
158 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
159 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
160 PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
161 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
162 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
163 &dv_pll1_regs->secctl);
164 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
165 writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
166 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
167 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
169 /* Post divider setting for PLL2 */
170 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
171 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
172 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
173 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
174 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
176 /* GoCmd for PostDivider to take effect */
177 writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
181 /* Wait for PLL to LOCK */
182 while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
186 dm365_waitloop(4100);
188 /* Enable the PLL2 */
189 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
191 /* do this after PLL's have been set up */
192 writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
193 &dv_sys_module_regs->peri_clkctl);
198 int dm365_ddr_setup(void)
200 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
201 clrbits_le32(&dv_sys_module_regs->vtpiocr,
202 VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
204 /* Set bit CLRZ (bit 13) */
205 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
207 /* Check VTP READY Status */
208 while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
211 /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
212 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
214 /* Set bit LOCK(bit7) */
215 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
218 * Powerdown VTP as it is locked (bit 6)
219 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
221 setbits_le32(&dv_sys_module_regs->vtpiocr,
222 VPTIO_IOPWRDN | VPTIO_PWRDN);
224 /* Wait for calibration to complete */
227 /* Set the DDR2 to synreset, then enable it again */
228 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
229 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
231 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
233 /* Program SDRAM Bank Config Register */
234 writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
235 &dv_ddr2_regs_ctrl->sdbcr);
236 writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
237 &dv_ddr2_regs_ctrl->sdbcr);
239 /* Program SDRAM Timing Control Register1 */
240 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
241 /* Program SDRAM Timing Control Register2 */
242 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
244 writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
246 writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
248 /* Program SDRAM Refresh Control Register */
249 writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
251 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
252 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
257 void dm365_vpss_sync_reset(void)
259 unsigned int PdNum = 0;
262 setbits_le32(&dv_sys_module_regs->vpss_clkctl,
263 VPSS_CLK_CTL_VPSS_CLKMD);
265 /* LPSC SyncReset DDR Clock Enable */
266 writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
267 ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
268 &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
270 writel((1 << PdNum), &dv_psc_regs->ptcmd);
272 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
274 while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
275 PSC_MD_STATE_MSK) == PSC_SYNCRESET))
279 void dm365_por_reset(void)
281 if (readl(&dv_pll0_regs->rstype) &
282 (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
283 dm365_vpss_sync_reset();
286 void dm365_psc_init(void)
289 unsigned char lpsc_start;
290 unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
291 unsigned int PdNum = 0;
296 for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
297 if (lpscgroup == 0) {
298 /* Enabling LPSC 3 to 28 SCR first */
299 lpsc_start = DAVINCI_LPSC_VPSSMSTR;
300 lpsc_end = DAVINCI_LPSC_TIMER1;
301 } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
302 lpsc_start = DAVINCI_LPSC_CFG5;
303 lpsc_end = DAVINCI_LPSC_VPSSMASTER;
305 lpsc_start = DAVINCI_LPSC_MJCP;
306 lpsc_end = DAVINCI_LPSC_HDVICP;
309 /* NEXT=0x3, Enable LPSC's */
310 for (i = lpsc_start; i <= lpsc_end; i++)
311 setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
314 * Program goctl to start transition sequence for LPSCs
315 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
318 writel((1 << PdNum), &dv_psc_regs->ptcmd);
321 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
323 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
327 /* Wait for MODSTAT = ENABLE from LPSC's */
328 for (i = lpsc_start; i <= lpsc_end; i++)
329 while (!((readl(&dv_psc_regs->mdstat[i]) &
330 PSC_MD_STATE_MSK) == PSC_ENABLE))
335 static void dm365_emif_init(void)
337 writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
338 writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
340 setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
342 writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
347 void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
350 clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
351 setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
354 __attribute__((weak))
355 void board_gpio_init(void)
360 #if defined(CONFIG_POST)
361 int post_log(char *format, ...)
367 void dm36x_lowlevel_init(ulong bootflag)
369 struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
370 (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
371 DAVINCI_UART_CTRL_BASE);
373 /* Mask all interrupts */
374 writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
375 writel(0x0, &dv_aintc_regs->eabase);
376 writel(0x0, &dv_aintc_regs->eint0);
377 writel(0x0, &dv_aintc_regs->eint1);
379 /* Clear all interrupts */
380 writel(0xffffffff, &dv_aintc_regs->fiq0);
381 writel(0xffffffff, &dv_aintc_regs->fiq1);
382 writel(0xffffffff, &dv_aintc_regs->irq0);
383 writel(0xffffffff, &dv_aintc_regs->irq1);
385 /* System PSC setup - enable all */
389 dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
390 dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
391 dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
392 dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
393 dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
396 dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
397 CONFIG_SYS_DM36x_PLL1_PREDIV);
398 dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
399 CONFIG_SYS_DM36x_PLL2_PREDIV);
404 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
405 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
408 * Fix Power and Emulation Management Register
409 * see sprufh2.pdf page 38 Table 22
411 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
412 DAVINCI_UART_PWREMU_MGMT_UTRST),
413 &davinci_uart_ctrl_regs->pwremu_mgmt);
421 #if defined(CONFIG_POST)
423 * Do memory tests, calls arch_memory_failure_handle()