2 * SoC-specific lowlevel code for tms320dm365 and similar chips
3 * Actually used for booting from NAND with nand_spl.
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <asm/arch/dm365_lowlevel.h>
30 #include <asm/arch/hardware.h>
32 void dm365_waitloop(unsigned long loopcnt)
36 for (i = 0; i < loopcnt; i++)
40 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
42 unsigned int clksrc = 0x0;
44 /* Power up the PLL */
45 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
47 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
48 setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
51 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
54 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
56 /* Set PLLEN=0 => PLL BYPASS MODE */
57 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
61 /* PLLRST=1(reset assert) */
62 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
66 /*Bring PLL out of Reset*/
67 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
69 /* Program the Multiper and Pre-Divider for PLL1 */
70 writel(pllmult, &dv_pll0_regs->pllm);
71 writel(prediv, &dv_pll0_regs->prediv);
73 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
74 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
75 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
76 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
77 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
78 &dv_pll0_regs->secctl);
79 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
80 writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
81 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
82 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
84 /* Program the PostDiv for PLL1 */
85 writel(0x8000, &dv_pll0_regs->postdiv);
87 /* Post divider setting for PLL1 */
88 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
89 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
90 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
91 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
92 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
93 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
94 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
95 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
96 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
100 /* Set the GOSET bit */
101 writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
105 /* Wait for PLL to LOCK */
106 while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
110 /* Enable the PLL Bit of PLLCTL*/
111 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
116 int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
118 unsigned int clksrc = 0x0;
120 /* Power up the PLL*/
121 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
124 * Select the Clock Mode as Onchip Oscilator or External Clock on
126 * VDB has input on MXI pin
128 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
129 setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
132 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
135 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
137 /* Set PLLEN=0 => PLL BYPASS MODE */
138 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
142 /* PLLRST=1(reset assert) */
143 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
147 /* Bring PLL out of Reset */
148 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
150 /* Program the Multiper and Pre-Divider for PLL2 */
151 writel(pllm, &dv_pll1_regs->pllm);
152 writel(prediv, &dv_pll1_regs->prediv);
154 writel(0x8000, &dv_pll1_regs->postdiv);
156 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
157 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
158 PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
159 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
160 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
161 &dv_pll1_regs->secctl);
162 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
163 writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
164 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
165 writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
167 /* Post divider setting for PLL2 */
168 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
169 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
170 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
171 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
172 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
174 /* GoCmd for PostDivider to take effect */
175 writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
179 /* Wait for PLL to LOCK */
180 while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
184 dm365_waitloop(4100);
186 /* Enable the PLL2 */
187 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
189 /* do this after PLL's have been set up */
190 writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
191 &dv_sys_module_regs->peri_clkctl);
196 int dm365_ddr_setup(void)
198 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
199 clrbits_le32(&dv_sys_module_regs->vtpiocr,
200 VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
202 /* Set bit CLRZ (bit 13) */
203 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
205 /* Check VTP READY Status */
206 while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
209 /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
210 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
212 /* Set bit LOCK(bit7) */
213 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
216 * Powerdown VTP as it is locked (bit 6)
217 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
219 setbits_le32(&dv_sys_module_regs->vtpiocr,
220 VPTIO_IOPWRDN | VPTIO_PWRDN);
222 /* Wait for calibration to complete */
225 /* Set the DDR2 to synreset, then enable it again */
226 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
227 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
229 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
231 /* Program SDRAM Bank Config Register */
232 writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
233 &dv_ddr2_regs_ctrl->sdbcr);
234 writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
235 &dv_ddr2_regs_ctrl->sdbcr);
237 /* Program SDRAM Timing Control Register1 */
238 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
239 /* Program SDRAM Timing Control Register2 */
240 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
242 writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
244 writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
246 /* Program SDRAM Refresh Control Register */
247 writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
249 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
250 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
255 void dm365_vpss_sync_reset(void)
257 unsigned int PdNum = 0;
260 setbits_le32(&dv_sys_module_regs->vpss_clkctl,
261 VPSS_CLK_CTL_VPSS_CLKMD);
263 /* LPSC SyncReset DDR Clock Enable */
264 writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
265 PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
267 writel((1 << PdNum), &dv_psc_regs->ptcmd);
269 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
271 while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) ==
276 void dm365_por_reset(void)
278 if (readl(&dv_pll0_regs->rstype) & 3)
279 dm365_vpss_sync_reset();
282 void dm365_psc_init(void)
285 unsigned char lpsc_start;
286 unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
287 unsigned int PdNum = 0;
292 for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
293 if (lpscgroup == 0) {
294 lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
296 } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
304 /* NEXT=0x3, Enable LPSC's */
305 for (i = lpsc_start; i <= lpsc_end; i++)
306 setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
309 * Program goctl to start transition sequence for LPSCs
310 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
313 writel((1 << PdNum), &dv_psc_regs->ptcmd);
316 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
318 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
322 /* Wait for MODSTAT = ENABLE from LPSC's */
323 for (i = lpsc_start; i <= lpsc_end; i++)
324 while (!((readl(&dv_psc_regs->mdstat[i]) &
325 PSC_MD_STATE_MSK) == 0x3))
330 static void dm365_emif_init(void)
332 writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
333 writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
335 setbits_le32(&davinci_emif_regs->nandfcr, 1);
337 writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
342 void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
345 clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
346 setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
349 __attribute__((weak))
350 void board_gpio_init(void)
355 #if defined(CONFIG_POST)
356 int post_log(char *format, ...)
362 void dm36x_lowlevel_init(ulong bootflag)
365 * copied from arch/arm/cpu/arm926ejs/start.S
367 * flush v4 I/D caches
370 asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
371 asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
374 * disable MMU stuff and caches
376 asm("mrc p15, 0, r0, c1, c0, 0");
377 /* clear bits 13, 9:8 (--V- --RS) */
378 asm("bic r0, r0, #0x00002300");
379 /* clear bits 7, 2:0 (B--- -CAM) */
380 asm("bic r0, r0, #0x00000087");
381 /* set bit 2 (A) Align */
382 asm("orr r0, r0, #0x00000002");
383 /* set bit 12 (I) I-Cache */
384 asm("orr r0, r0, #0x00001000");
385 asm("mcr p15, 0, r0, c1, c0, 0");
387 /* Mask all interrupts */
388 writel(0x04, &dv_aintc_regs->intctl);
389 writel(0x0, &dv_aintc_regs->eabase);
390 writel(0x0, &dv_aintc_regs->eint0);
391 writel(0x0, &dv_aintc_regs->eint1);
393 /* Clear all interrupts */
394 writel(0xffffffff, &dv_aintc_regs->fiq0);
395 writel(0xffffffff, &dv_aintc_regs->fiq1);
396 writel(0xffffffff, &dv_aintc_regs->irq0);
397 writel(0xffffffff, &dv_aintc_regs->irq1);
399 /* System PSC setup - enable all */
403 dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
404 dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
405 dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
406 dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
407 dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
410 dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
411 CONFIG_SYS_DM36x_PLL1_PREDIV);
412 dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
413 CONFIG_SYS_DM36x_PLL2_PREDIV);
418 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
419 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
422 * Fix Power and Emulation Management Register
423 * see sprufh2.pdf page 38 Table 22
425 writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
432 #if defined(CONFIG_POST)
434 * Do memory tests, calls arch_memory_failure_handle()