2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/da850_lowlevel.h>
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/davinci_misc.h>
31 #include <asm/arch/ddr2_defs.h>
32 #include <asm/arch/emif_defs.h>
33 #include <asm/arch/pll_defs.h>
35 #if defined(CONFIG_SYS_DA850_PLL_INIT)
36 void da850_waitloop(unsigned long loopcnt)
40 for (i = 0; i < loopcnt; i++)
44 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
46 if (reg == davinci_pllc0_regs)
47 /* Unlock PLL registers. */
48 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
51 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
54 clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
55 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
56 clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
58 /* Set PLLEN=0 => PLL BYPASS MODE */
59 clrbits_le32(®->pllctl, PLLCTL_PLLEN);
63 if (reg == davinci_pllc0_regs) {
65 * Select the Clock Mode bit 8 as External Clock or On Chip
68 dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
69 setbits_le32(®->pllctl,
70 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
73 /* Clear PLLRST bit to reset the PLL */
74 clrbits_le32(®->pllctl, PLLCTL_PLLRST);
76 /* Disable the PLL output */
77 setbits_le32(®->pllctl, PLLCTL_PLLDIS);
79 /* PLL initialization sequence */
81 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
84 clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
86 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
87 clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
89 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
90 /* program the prediv */
91 if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
92 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
96 /* Program the required multiplier value in PLLM */
97 writel(pllmult, ®->pllm);
99 /* program the postdiv */
100 if (reg == davinci_pllc0_regs)
101 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
104 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
108 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
109 * no GO operation is currently in progress
111 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
114 if (reg == davinci_pllc0_regs) {
115 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
116 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
117 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
118 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
119 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
120 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
121 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
123 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
124 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
125 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
129 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
132 setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
135 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
136 * (completion of phase alignment).
138 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
141 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
144 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
145 setbits_le32(®->pllctl, PLLCTL_PLLRST);
147 /* Wait for PLL to lock. See PLL spec for PLL lock time */
148 da850_waitloop(2400);
151 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
154 setbits_le32(®->pllctl, PLLCTL_PLLEN);
158 * clear EMIFA and EMIFB clock source settings, let them
161 if (reg == davinci_pllc0_regs)
162 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
163 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
167 #endif /* CONFIG_SYS_DA850_PLL_INIT */
169 #if defined(CONFIG_SYS_DA850_DDR_INIT)
170 int da850_ddr_setup(void)
174 /* Enable the Clock to DDR2/mDDR */
175 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
177 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
178 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
179 /* Begin VTP Calibration */
180 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
181 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
182 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
183 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
186 /* Polling READY bit to see when VTP calibration is done */
187 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
188 while ((tmp & VTP_READY) != VTP_READY)
189 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
191 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
192 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
194 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
197 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
198 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
199 (1 << DDR_SLEW_CMOSEN_BIT));
202 * SDRAM Configuration Register (SDCR):
203 * First set the BOOTUNLOCK bit to make configuration bits
206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
209 * Write the new value of these bits and clear BOOTUNLOCK.
210 * At the same time, set the TIMUNLOCK bit to allow changing
211 * the timing registers
213 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
214 tmp &= ~DV_DDR_BOOTUNLOCK;
215 tmp |= DV_DDR_TIMUNLOCK;
216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
218 /* write memory configuration and timing */
219 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
220 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
221 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
223 /* clear the TIMUNLOCK bit and write the value of the CL field */
224 tmp &= ~DV_DDR_TIMUNLOCK;
225 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
228 * LPMODEN and MCLKSTOPEN must be set!
229 * Without this bits set, PSC don;t switch states !!
231 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
232 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
233 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
234 &dv_ddr2_regs_ctrl->sdrcr);
236 /* SyncReset the Clock to EMIF3A SDRAM */
237 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
238 /* Enable the Clock to EMIF3A SDRAM */
239 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
241 /* disable self refresh */
242 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
243 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
244 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
248 #endif /* CONFIG_SYS_DA850_DDR_INIT */
250 __attribute__((weak))
251 void board_gpio_init(void)
256 int arch_cpu_init(void)
258 /* Unlock kick registers */
259 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
260 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
262 dv_maskbits(&davinci_syscfg_regs->suspsrc,
263 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
265 /* configure pinmux settings */
266 if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
269 #if defined(CONFIG_SYS_DA850_PLL_INIT)
271 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
272 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
274 /* setup CSn config */
275 #if defined(CONFIG_SYS_DA850_CS2CFG)
276 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
278 #if defined(CONFIG_SYS_DA850_CS3CFG)
279 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
282 da8xx_configure_lpsc_items(lpsc, lpsc_size);
288 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
289 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
292 * Fix Power and Emulation Management Register
293 * see sprufw3a.pdf page 37 Table 24
295 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
296 DAVINCI_UART_PWREMU_MGMT_UTRST),
297 &davinci_uart2_ctrl_regs->pwremu_mgmt);
299 #if defined(CONFIG_SYS_DA850_DDR_INIT)