2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/da850_lowlevel.h>
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/davinci_misc.h>
31 #include <asm/arch/ddr2_defs.h>
32 #include <asm/arch/emif_defs.h>
33 #include <asm/arch/pll_defs.h>
35 void da850_waitloop(unsigned long loopcnt)
39 for (i = 0; i < loopcnt; i++)
43 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
45 if (reg == davinci_pllc0_regs)
46 /* Unlock PLL registers. */
47 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
50 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
53 clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
54 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
55 clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
57 /* Set PLLEN=0 => PLL BYPASS MODE */
58 clrbits_le32(®->pllctl, PLLCTL_PLLEN);
62 if (reg == davinci_pllc0_regs) {
64 * Select the Clock Mode bit 8 as External Clock or On Chip
67 dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
68 setbits_le32(®->pllctl,
69 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
72 /* Clear PLLRST bit to reset the PLL */
73 clrbits_le32(®->pllctl, PLLCTL_PLLRST);
75 /* Disable the PLL output */
76 setbits_le32(®->pllctl, PLLCTL_PLLDIS);
78 /* PLL initialization sequence */
80 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
83 clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
85 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
86 clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
88 /* Program the required multiplier value in PLLM */
89 writel(pllmult, ®->pllm);
91 /* program the postdiv */
92 if (reg == davinci_pllc0_regs)
93 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
96 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
100 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
101 * no GO operation is currently in progress
103 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
106 if (reg == davinci_pllc0_regs) {
107 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
111 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
112 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
113 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
115 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
116 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
117 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
121 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
124 setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
127 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
128 * (completion of phase alignment).
130 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
133 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
136 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
137 setbits_le32(®->pllctl, PLLCTL_PLLRST);
139 /* Wait for PLL to lock. See PLL spec for PLL lock time */
140 da850_waitloop(2400);
143 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
146 setbits_le32(®->pllctl, PLLCTL_PLLEN);
150 * clear EMIFA and EMIFB clock source settings, let them
153 if (reg == davinci_pllc0_regs)
154 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
155 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
160 int da850_ddr_setup(void)
164 /* Enable the Clock to DDR2/mDDR */
165 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
167 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
168 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
169 /* Begin VTP Calibration */
170 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
171 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
172 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
173 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
174 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
176 /* Polling READY bit to see when VTP calibration is done */
177 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
178 while ((tmp & VTP_READY) != VTP_READY)
179 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
181 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
182 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
188 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
189 (1 << DDR_SLEW_CMOSEN_BIT));
192 * SDRAM Configuration Register (SDCR):
193 * First set the BOOTUNLOCK bit to make configuration bits
196 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
199 * Write the new value of these bits and clear BOOTUNLOCK.
200 * At the same time, set the TIMUNLOCK bit to allow changing
201 * the timing registers
203 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
204 tmp &= ~DV_DDR_BOOTUNLOCK;
205 tmp |= DV_DDR_TIMUNLOCK;
206 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
208 /* write memory configuration and timing */
209 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
210 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
211 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
213 /* clear the TIMUNLOCK bit and write the value of the CL field */
214 tmp &= ~DV_DDR_TIMUNLOCK;
215 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
218 * LPMODEN and MCLKSTOPEN must be set!
219 * Without this bits set, PSC don;t switch states !!
221 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
222 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
223 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
224 &dv_ddr2_regs_ctrl->sdrcr);
226 /* SyncReset the Clock to EMIF3A SDRAM */
227 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
228 /* Enable the Clock to EMIF3A SDRAM */
229 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
231 /* disable self refresh */
232 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
233 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
234 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
239 __attribute__((weak))
240 void board_gpio_init(void)
245 /* pinmux_resource[] vector is defined in the board specific file */
246 extern const struct pinmux_resource pinmuxes[];
247 extern const int pinmuxes_size;
249 int arch_cpu_init(void)
251 /* Unlock kick registers */
252 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
253 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
255 dv_maskbits(&davinci_syscfg_regs->suspsrc,
256 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
258 /* configure pinmux settings */
259 if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
263 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
264 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
269 /* setup CSn config */
270 #if defined(CONFIG_SYS_DA850_CS2CFG)
271 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
273 #if defined(CONFIG_SYS_DA850_CS3CFG)
274 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
277 lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
278 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
279 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
282 * Fix Power and Emulation Management Register
283 * see sprufw3a.pdf page 37 Table 24
285 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
286 DAVINCI_UART_PWREMU_MGMT_UTRST),
287 &davinci_uart2_ctrl_regs->pwremu_mgmt);