2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/da850_lowlevel.h>
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/ddr2_defs.h>
31 #include <asm/arch/emif_defs.h>
33 void da850_waitloop(unsigned long loopcnt)
37 for (i = 0; i < loopcnt; i++)
41 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
43 if (reg == davinci_pllc0_regs)
44 /* Unlock PLL registers. */
45 clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
48 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
51 clrbits_le32(®->pllctl, 0x00000020);
52 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
53 clrbits_le32(®->pllctl, 0x00000200);
55 /* Set PLLEN=0 => PLL BYPASS MODE */
56 clrbits_le32(®->pllctl, 0x00000001);
60 if (reg == davinci_pllc0_regs) {
62 * Select the Clock Mode bit 8 as External Clock or On Chip
65 dv_maskbits(®->pllctl, 0xFFFFFEFF);
66 setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
69 /* Clear PLLRST bit to reset the PLL */
70 clrbits_le32(®->pllctl, 0x00000008);
72 /* Disable the PLL output */
73 setbits_le32(®->pllctl, 0x00000010);
75 /* PLL initialization sequence */
77 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
80 clrbits_le32(®->pllctl, 0x00000002);
82 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
83 clrbits_le32(®->pllctl, 0x00000010);
85 /* Program the required multiplier value in PLLM */
86 writel(pllmult, ®->pllm);
88 /* program the postdiv */
89 if (reg == davinci_pllc0_regs)
90 writel((0x8000 | CONFIG_SYS_DA850_PLL0_POSTDIV),
93 writel((0x8000 | CONFIG_SYS_DA850_PLL1_POSTDIV),
97 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
98 * no GO operation is currently in progress
100 while ((readl(®->pllstat) & 0x1) == 1)
103 if (reg == davinci_pllc0_regs) {
104 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
105 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
106 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
107 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
112 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
113 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
114 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
118 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
121 setbits_le32(®->pllcmd, 0x01);
124 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
125 * (completion of phase alignment).
127 while ((readl(®->pllstat) & 0x1) == 1)
130 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
133 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
134 setbits_le32(®->pllctl, 0x00000008);
136 /* Wait for PLL to lock. See PLL spec for PLL lock time */
137 da850_waitloop(2400);
140 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
143 setbits_le32(®->pllctl, 0x00000001);
147 * clear EMIFA and EMIFB clock source settings, let them
150 if (reg == davinci_pllc0_regs)
151 dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
156 int da850_ddr_setup(unsigned int freq)
160 /* Enable the Clock to DDR2/mDDR */
161 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
163 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
164 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
165 /* Begin VTP Calibration */
166 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
167 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
168 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
169 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
170 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
172 /* Polling READY bit to see when VTP calibration is done */
173 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
174 while ((tmp & VTP_READY) != VTP_READY)
175 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
177 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
178 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
180 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
183 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
184 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
185 (1 << DDR_SLEW_CMOSEN_BIT));
188 * SDRAM Configuration Register (SDCR):
189 * First set the BOOTUNLOCK bit to make configuration bits
192 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
195 * Write the new value of these bits and clear BOOTUNLOCK.
196 * At the same time, set the TIMUNLOCK bit to allow changing
197 * the timing registers
199 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
200 tmp &= ~(0x1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT);
201 tmp |= (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
202 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
204 /* write memory configuration and timing */
205 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
206 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
207 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
209 /* clear the TIMUNLOCK bit and write the value of the CL field */
210 tmp &= ~(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
211 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
214 * LPMODEN and MCLKSTOPEN must be set!
215 * Without this bits set, PSC don;t switch states !!
217 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
218 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
219 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
220 &dv_ddr2_regs_ctrl->sdrcr);
222 /* SyncReset the Clock to EMIF3A SDRAM */
223 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
224 /* Enable the Clock to EMIF3A SDRAM */
225 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
227 /* disable self refresh */
228 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
229 writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
234 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
237 clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
238 setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
241 __attribute__((weak))
242 void board_gpio_init(void)
247 #if defined(CONFIG_NAND_SPL)
250 __attribute__((noreturn)) void (*uboot)(void);
252 /* copy image from NOR to RAM */
253 memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
254 (void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
255 CONFIG_SYS_NAND_U_BOOT_SIZE);
257 /* and jump to it ... */
258 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
263 #if defined(CONFIG_NAND_SPL)
264 void board_init_f(ulong bootflag)
266 int arch_cpu_init(void)
270 * copied from arch/arm/cpu/arm926ejs/start.S
272 * flush v4 I/D caches
275 asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
276 asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
279 * disable MMU stuff and caches
281 asm("mrc p15, 0, r0, c1, c0, 0");
282 /* clear bits 13, 9:8 (--V- --RS) */
283 asm("bic r0, r0, #0x00002300");
284 /* clear bits 7, 2:0 (B--- -CAM) */
285 asm("bic r0, r0, #0x00000087");
286 /* set bit 2 (A) Align */
287 asm("orr r0, r0, #0x00000002");
288 /* set bit 12 (I) I-Cache */
289 asm("orr r0, r0, #0x00001000");
290 asm("mcr p15, 0, r0, c1, c0, 0");
292 /* Unlock kick registers */
293 writel(0x83e70b13, &davinci_syscfg_regs->kick0);
294 writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
296 dv_maskbits(&davinci_syscfg_regs->suspsrc,
297 ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
300 da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
301 da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
302 da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
303 da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
304 da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
305 da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
306 da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
307 da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
308 da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
309 da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
310 da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
311 da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
312 da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
313 da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
314 da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
315 da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
316 da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
317 da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
318 da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
319 da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
322 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
323 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
328 /* setup CSn config */
329 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
330 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
332 lpsc_on(DAVINCI_LPSC_UART2);
333 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
334 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
337 * Fix Power and Emulation Management Register
338 * see sprufw3a.pdf page 37 Table 24
340 writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
341 (CONFIG_SYS_NS16550_COM1 + 0x30));
342 #if defined(CONFIG_NAND_SPL)
344 da850_ddr_setup(132);
346 puts("boot u-boot ...\n");
350 da850_ddr_setup(132);