2 * Copyright (C) 2004 Texas Instruments.
3 * Copyright (C) 2009 David Brownell
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/arch/hardware.h>
28 /* offsets from PLL controller base */
29 #define PLLC_PLLCTL 0x100
30 #define PLLC_PLLM 0x110
31 #define PLLC_PREDIV 0x114
32 #define PLLC_PLLDIV1 0x118
33 #define PLLC_PLLDIV2 0x11c
34 #define PLLC_PLLDIV3 0x120
35 #define PLLC_POSTDIV 0x128
36 #define PLLC_BPDIV 0x12c
37 #define PLLC_PLLDIV4 0x160
38 #define PLLC_PLLDIV5 0x164
39 #define PLLC_PLLDIV6 0x168
40 #define PLLC_PLLDIV7 0x16c
41 #define PLLC_PLLDIV8 0x170
42 #define PLLC_PLLDIV9 0x174
44 #define BIT(x) (1 << (x))
46 /* SOC-specific pll info */
47 #ifdef CONFIG_SOC_DM355
48 #define ARM_PLLDIV PLLC_PLLDIV1
49 #define DDR_PLLDIV PLLC_PLLDIV1
52 #ifdef CONFIG_SOC_DM644X
53 #define ARM_PLLDIV PLLC_PLLDIV2
54 #define DSP_PLLDIV PLLC_PLLDIV1
55 #define DDR_PLLDIV PLLC_PLLDIV2
58 #ifdef CONFIG_SOC_DM646X
59 #define DSP_PLLDIV PLLC_PLLDIV1
60 #define ARM_PLLDIV PLLC_PLLDIV2
61 #define DDR_PLLDIV PLLC_PLLDIV1
64 #ifdef CONFIG_SOC_DA8XX
65 unsigned int sysdiv[9] = {
66 PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
67 PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
70 int clk_get(enum davinci_clk_ids id)
76 unsigned int pll_base;
78 pll_out = CONFIG_SYS_OSCIN_FREQ;
80 if (id == DAVINCI_AUXCLK_CLKID)
84 pll_base = (unsigned int)davinci_pllc1_regs;
86 pll_base = (unsigned int)davinci_pllc0_regs;
91 * Lets keep this simple. Combining operations can result in
92 * unexpected approximations
94 pre_div = (readl(pll_base + PLLC_PREDIV) &
95 DAVINCI_PLLC_DIV_MASK) + 1;
96 pllm = readl(pll_base + PLLC_PLLM) + 1;
101 if (id == DAVINCI_PLLM_CLKID)
104 post_div = (readl(pll_base + PLLC_POSTDIV) &
105 DAVINCI_PLLC_DIV_MASK) + 1;
109 if (id == DAVINCI_PLLC_CLKID)
112 pll_out /= (readl(pll_base + sysdiv[id - 1]) &
113 DAVINCI_PLLC_DIV_MASK) + 1;
118 #ifdef CONFIG_DISPLAY_CPUINFO
119 int print_cpuinfo(void)
121 printf("Cores: ARM %d MHz",
122 clk_get(DAVINCI_ARM_CLKID) / 1000000);
123 printf("\nDDR: %d MHz\n",
124 /* DDR PHY uses an x2 input clock */
125 clk_get(0x10001) / 1000000);
129 #else /* CONFIG_SOC_DA8XX */
131 #ifdef CONFIG_DISPLAY_CPUINFO
133 static unsigned pll_div(volatile void *pllbase, unsigned offset)
137 div = REG(pllbase + offset);
138 return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
141 static inline unsigned pll_prediv(volatile void *pllbase)
143 #ifdef CONFIG_SOC_DM355
144 /* this register read seems to fail on pll0 */
145 if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
148 return pll_div(pllbase, PLLC_PREDIV);
149 #elif defined(CONFIG_SOC_DM365)
150 return pll_div(pllbase, PLLC_PREDIV);
155 static inline unsigned pll_postdiv(volatile void *pllbase)
157 #if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
158 return pll_div(pllbase, PLLC_POSTDIV);
159 #elif defined(CONFIG_SOC_DM6446)
160 if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
161 return pll_div(pllbase, PLLC_POSTDIV);
166 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
168 volatile void *pllbase = (volatile void *) pll_addr;
169 #ifdef CONFIG_SOC_DM646X
170 unsigned base = CFG_REFCLK_FREQ / 1000;
172 unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
175 /* the PLL might be bypassed */
176 if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
177 base /= pll_prediv(pllbase);
178 #if defined(CONFIG_SOC_DM365)
179 base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
181 base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
183 base /= pll_postdiv(pllbase);
185 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
188 int print_cpuinfo(void)
190 /* REVISIT fetch and display CPU ID and revision information
191 * too ... that will matter as more revisions appear.
193 #if defined(CONFIG_SOC_DM365)
194 printf("Cores: ARM %d MHz",
195 pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
197 printf("Cores: ARM %d MHz",
198 pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
202 printf(", DSP %d MHz",
203 pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
206 printf("\nDDR: %d MHz\n",
207 /* DDR PHY uses an x2 input clock */
208 #if defined(CONFIG_SOC_DM365)
209 pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
212 pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
218 #ifdef DAVINCI_DM6467EVM
219 unsigned int davinci_arm_clk_get()
221 return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
225 #if defined(CONFIG_SOC_DM365)
226 unsigned int davinci_clk_get(unsigned int div)
228 return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
231 #endif /* CONFIG_DISPLAY_CPUINFO */
232 #endif /* !CONFIG_SOC_DA8XX */
235 * Initializes on-chip ethernet controllers.
236 * to override, implement board_eth_init()
238 int cpu_eth_init(bd_t *bis)
240 #if defined(CONFIG_DRIVER_TI_EMAC)
241 davinci_emac_initialize();