2 * Copyright (C) 2004 Texas Instruments.
3 * Copyright (C) 2009 David Brownell
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/arch/hardware.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* offsets from PLL controller base */
31 #define PLLC_PLLCTL 0x100
32 #define PLLC_PLLM 0x110
33 #define PLLC_PREDIV 0x114
34 #define PLLC_PLLDIV1 0x118
35 #define PLLC_PLLDIV2 0x11c
36 #define PLLC_PLLDIV3 0x120
37 #define PLLC_POSTDIV 0x128
38 #define PLLC_BPDIV 0x12c
39 #define PLLC_PLLDIV4 0x160
40 #define PLLC_PLLDIV5 0x164
41 #define PLLC_PLLDIV6 0x168
42 #define PLLC_PLLDIV7 0x16c
43 #define PLLC_PLLDIV8 0x170
44 #define PLLC_PLLDIV9 0x174
46 #define BIT(x) (1 << (x))
48 /* SOC-specific pll info */
49 #ifdef CONFIG_SOC_DM355
50 #define ARM_PLLDIV PLLC_PLLDIV1
51 #define DDR_PLLDIV PLLC_PLLDIV1
54 #ifdef CONFIG_SOC_DM644X
55 #define ARM_PLLDIV PLLC_PLLDIV2
56 #define DSP_PLLDIV PLLC_PLLDIV1
57 #define DDR_PLLDIV PLLC_PLLDIV2
60 #ifdef CONFIG_SOC_DM646X
61 #define DSP_PLLDIV PLLC_PLLDIV1
62 #define ARM_PLLDIV PLLC_PLLDIV2
63 #define DDR_PLLDIV PLLC_PLLDIV1
66 #ifdef CONFIG_SOC_DA8XX
67 unsigned int sysdiv[9] = {
68 PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
69 PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
72 int clk_get(enum davinci_clk_ids id)
78 unsigned int pll_base;
80 pll_out = CONFIG_SYS_OSCIN_FREQ;
82 if (id == DAVINCI_AUXCLK_CLKID)
86 pll_base = (unsigned int)davinci_pllc1_regs;
88 pll_base = (unsigned int)davinci_pllc0_regs;
93 * Lets keep this simple. Combining operations can result in
94 * unexpected approximations
96 pre_div = (readl(pll_base + PLLC_PREDIV) &
97 DAVINCI_PLLC_DIV_MASK) + 1;
98 pllm = readl(pll_base + PLLC_PLLM) + 1;
103 if (id == DAVINCI_PLLM_CLKID)
106 post_div = (readl(pll_base + PLLC_POSTDIV) &
107 DAVINCI_PLLC_DIV_MASK) + 1;
111 if (id == DAVINCI_PLLC_CLKID)
114 pll_out /= (readl(pll_base + sysdiv[id - 1]) &
115 DAVINCI_PLLC_DIV_MASK) + 1;
120 #else /* CONFIG_SOC_DA8XX */
122 static unsigned pll_div(volatile void *pllbase, unsigned offset)
126 div = REG(pllbase + offset);
127 return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
130 static inline unsigned pll_prediv(volatile void *pllbase)
132 #ifdef CONFIG_SOC_DM355
133 /* this register read seems to fail on pll0 */
134 if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
137 return pll_div(pllbase, PLLC_PREDIV);
138 #elif defined(CONFIG_SOC_DM365)
139 return pll_div(pllbase, PLLC_PREDIV);
144 static inline unsigned pll_postdiv(volatile void *pllbase)
146 #if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
147 return pll_div(pllbase, PLLC_POSTDIV);
148 #elif defined(CONFIG_SOC_DM6446)
149 if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
150 return pll_div(pllbase, PLLC_POSTDIV);
155 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
157 volatile void *pllbase = (volatile void *) pll_addr;
158 #ifdef CONFIG_SOC_DM646X
159 unsigned base = CONFIG_REFCLK_FREQ / 1000;
161 unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
164 /* the PLL might be bypassed */
165 if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
166 base /= pll_prediv(pllbase);
167 #if defined(CONFIG_SOC_DM365)
168 base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
170 base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
172 base /= pll_postdiv(pllbase);
174 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
177 #ifdef DAVINCI_DM6467EVM
178 unsigned int davinci_arm_clk_get()
180 return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
184 #if defined(CONFIG_SOC_DM365)
185 unsigned int davinci_clk_get(unsigned int div)
187 return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
190 #endif /* !CONFIG_SOC_DA8XX */
192 int set_cpu_clk_info(void)
194 #ifdef CONFIG_SOC_DA8XX
195 gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
196 /* DDR PHY uses an x2 input clock */
197 gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
200 unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
201 #if defined(CONFIG_SOC_DM365)
202 pllbase = DAVINCI_PLL_CNTRL1_BASE;
204 gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
207 gd->bd->bi_dsp_freq =
208 pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
210 gd->bd->bi_dsp_freq = 0;
213 pllbase = DAVINCI_PLL_CNTRL1_BASE;
214 #if defined(CONFIG_SOC_DM365)
215 pllbase = DAVINCI_PLL_CNTRL0_BASE;
217 gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
223 * Initializes on-chip ethernet controllers.
224 * to override, implement board_eth_init()
226 int cpu_eth_init(bd_t *bis)
228 #if defined(CONFIG_DRIVER_TI_EMAC)
229 davinci_emac_initialize();