2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/at91_wdt.h>
17 #include <asm/arch/at91_pio.h>
18 #include <asm/arch/at91_matrix.h>
19 #include <asm/arch/at91sam9_sdramc.h>
20 #include <asm/arch/at91sam9_smc.h>
21 #include <asm/arch/at91_rstc.h>
22 #ifdef CONFIG_ATMEL_LEGACY
23 #include <asm/arch/at91sam9_matrix.h>
25 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
26 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
30 .word CONFIG_SYS_TEXT_BASE
33 .type lowlevel_init,function
36 mov r5, pc /* r5 = POS1 + 4 current */
38 ldr r0, =POS1 /* r0 = POS1 compile */
40 sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
41 sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
42 sub r5, r5, #4 /* r1 = text base - current */
44 /* memory control configuration 1 */
61 /* ----------------------------------------------------------------------------
63 * ----------------------------------------------------------------------------
64 * - Check if the PLL is already initialized
65 * ----------------------------------------------------------------------------
67 ldr r1, =(AT91_ASM_PMC_MCKR)
73 /* ---------------------------------------------------------------------------
74 * - Enable the Main Oscillator
75 * ---------------------------------------------------------------------------
77 ldr r1, =(AT91_ASM_PMC_MOR)
78 ldr r2, =(AT91_ASM_PMC_SR)
79 /* Main oscillator Enable register PMC_MOR: */
80 ldr r0, =CONFIG_SYS_MOR_VAL
83 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
84 mov r4, #AT91_PMC_IXR_MOSCS
88 cmp r3, #AT91_PMC_IXR_MOSCS
91 /* ----------------------------------------------------------------------------
93 * ----------------------------------------------------------------------------
95 * ----------------------------------------------------------------------------
97 ldr r1, =(AT91_ASM_PMC_PLLAR)
98 ldr r0, =CONFIG_SYS_PLLAR_VAL
101 /* Reading the PMC Status register to detect when the PLLA is locked */
102 mov r4, #AT91_PMC_IXR_LOCKA
106 cmp r3, #AT91_PMC_IXR_LOCKA
109 /* ----------------------------------------------------------------------------
111 * ----------------------------------------------------------------------------
112 * - Switch on the Main Oscillator
113 * ----------------------------------------------------------------------------
115 ldr r1, =(AT91_ASM_PMC_MCKR)
117 /* -Master Clock Controller register PMC_MCKR */
118 ldr r0, =CONFIG_SYS_MCKR1_VAL
121 /* Reading the PMC Status to detect when the Master clock is ready */
122 mov r4, #AT91_PMC_IXR_MCKRDY
126 cmp r3, #AT91_PMC_IXR_MCKRDY
129 ldr r0, =CONFIG_SYS_MCKR2_VAL
132 /* Reading the PMC Status to detect when the Master clock is ready */
133 mov r4, #AT91_PMC_IXR_MCKRDY
137 cmp r3, #AT91_PMC_IXR_MCKRDY
141 /* ----------------------------------------------------------------------------
142 * - memory control configuration 2
143 * ----------------------------------------------------------------------------
145 ldr r0, =(AT91_ASM_SDRAMC_TR)
167 /* everything is fine now */
173 .word AT91_ASM_WDT_MR
174 .word CONFIG_SYS_WDTC_WDMR_VAL
175 /* configure PIOx as EBI0 D[16-31] */
176 #if defined(CONFIG_AT91SAM9263)
177 .word AT91_ASM_PIOD_PDR
178 .word CONFIG_SYS_PIOD_PDR_VAL1
179 .word AT91_ASM_PIOD_PUDR
180 .word CONFIG_SYS_PIOD_PPUDR_VAL
181 .word AT91_ASM_PIOD_ASR
182 .word CONFIG_SYS_PIOD_PPUDR_VAL
183 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
184 || defined(CONFIG_AT91SAM9G20)
185 .word AT91_ASM_PIOC_PDR
186 .word CONFIG_SYS_PIOC_PDR_VAL1
187 .word AT91_ASM_PIOC_PUDR
188 .word CONFIG_SYS_PIOC_PPUDR_VAL
190 .word AT91_ASM_MATRIX_CSA0
191 .word CONFIG_SYS_MATRIX_EBICSA_VAL
194 .word AT91_ASM_SMC_MODE0
195 .word CONFIG_SYS_SMC0_MODE0_VAL
197 .word AT91_ASM_SMC_CYCLE0
198 .word CONFIG_SYS_SMC0_CYCLE0_VAL
200 .word AT91_ASM_SMC_PULSE0
201 .word CONFIG_SYS_SMC0_PULSE0_VAL
203 .word AT91_ASM_SMC_SETUP0
204 .word CONFIG_SYS_SMC0_SETUP0_VAL
207 .word AT91_ASM_SDRAMC_MR
208 .word CONFIG_SYS_SDRC_MR_VAL1
209 .word AT91_ASM_SDRAMC_TR
210 .word CONFIG_SYS_SDRC_TR_VAL1
211 .word AT91_ASM_SDRAMC_CR
212 .word CONFIG_SYS_SDRC_CR_VAL
213 .word AT91_ASM_SDRAMC_MDR
214 .word CONFIG_SYS_SDRC_MDR_VAL
215 .word AT91_ASM_SDRAMC_MR
216 .word CONFIG_SYS_SDRC_MR_VAL2
217 .word CONFIG_SYS_SDRAM_BASE
218 .word CONFIG_SYS_SDRAM_VAL1
219 .word AT91_ASM_SDRAMC_MR
220 .word CONFIG_SYS_SDRC_MR_VAL3
221 .word CONFIG_SYS_SDRAM_BASE
222 .word CONFIG_SYS_SDRAM_VAL2
223 .word CONFIG_SYS_SDRAM_BASE
224 .word CONFIG_SYS_SDRAM_VAL3
225 .word CONFIG_SYS_SDRAM_BASE
226 .word CONFIG_SYS_SDRAM_VAL4
227 .word CONFIG_SYS_SDRAM_BASE
228 .word CONFIG_SYS_SDRAM_VAL5
229 .word CONFIG_SYS_SDRAM_BASE
230 .word CONFIG_SYS_SDRAM_VAL6
231 .word CONFIG_SYS_SDRAM_BASE
232 .word CONFIG_SYS_SDRAM_VAL7
233 .word CONFIG_SYS_SDRAM_BASE
234 .word CONFIG_SYS_SDRAM_VAL8
235 .word CONFIG_SYS_SDRAM_BASE
236 .word CONFIG_SYS_SDRAM_VAL9
237 .word AT91_ASM_SDRAMC_MR
238 .word CONFIG_SYS_SDRC_MR_VAL4
239 .word CONFIG_SYS_SDRAM_BASE
240 .word CONFIG_SYS_SDRAM_VAL10
241 .word AT91_ASM_SDRAMC_MR
242 .word CONFIG_SYS_SDRC_MR_VAL5
243 .word CONFIG_SYS_SDRAM_BASE
244 .word CONFIG_SYS_SDRAM_VAL11
245 .word AT91_ASM_SDRAMC_TR
246 .word CONFIG_SYS_SDRC_TR_VAL2
247 .word CONFIG_SYS_SDRAM_BASE
248 .word CONFIG_SYS_SDRAM_VAL12
249 /* User reset enable*/
250 .word AT91_ASM_RSTC_MR
251 .word CONFIG_SYS_RSTC_RMR_VAL
252 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
253 /* MATRIX_MCFG - REMAP all masters */
254 .word AT91_ASM_MATRIX_MCFG