2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/io.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/clk.h>
20 static unsigned long cpu_clk_rate_hz;
21 static unsigned long main_clk_rate_hz;
22 static unsigned long mck_rate_hz;
23 static unsigned long plla_rate_hz;
24 static unsigned long pllb_rate_hz;
25 static u32 at91_pllb_usb_init;
27 unsigned long get_cpu_clk_rate(void)
29 return cpu_clk_rate_hz;
32 unsigned long get_main_clk_rate(void)
34 return main_clk_rate_hz;
37 unsigned long get_mck_clk_rate(void)
42 unsigned long get_plla_clk_rate(void)
47 unsigned long get_pllb_clk_rate(void)
52 u32 get_pllb_init(void)
54 return at91_pllb_usb_init;
57 static unsigned long at91_css_to_rate(unsigned long css)
60 case AT91_PMC_MCKR_CSS_SLOW:
61 return AT91_SLOW_CLOCK;
62 case AT91_PMC_MCKR_CSS_MAIN:
63 return main_clk_rate_hz;
64 case AT91_PMC_MCKR_CSS_PLLA:
66 case AT91_PMC_MCKR_CSS_PLLB:
73 #ifdef CONFIG_USB_ATMEL
74 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
76 unsigned i, div = 0, mul = 0, diff = 1 << 30;
77 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
79 /* PLL output max 240 MHz (or 180 MHz per errata) */
80 if (out_freq > 240000000)
83 for (i = 1; i < 256; i++) {
88 * PLL input between 1MHz and 32MHz per spec, but lower
89 * frequences seem necessary in some cases so allow 100K.
90 * Warning: some newer products need 2MHz min.
92 input = main_freq / i;
93 #if defined(CONFIG_AT91SAM9G20)
102 mul1 = out_freq / input;
103 #if defined(CONFIG_AT91SAM9G20)
112 diff1 = out_freq - input * mul1;
123 if (i == 256 && diff > (out_freq >> 5))
125 return ret | ((mul - 1) << 16) | div;
131 static u32 at91_pll_rate(u32 freq, u32 reg)
136 mul = (reg >> 16) & 0x7ff;
146 int at91_clock_init(unsigned long main_clock)
149 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
150 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
153 * When the bootloader initialized the main oscillator correctly,
154 * there's no problem using the cycle counter. But if it didn't,
155 * or when using oscillator bypass mode, we must be told the speed
160 tmp = readl(&pmc->mcfr);
161 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
162 tmp &= AT91_PMC_MCFR_MAINF_MASK;
163 main_clock = tmp * (AT91_SLOW_CLOCK / 16);
166 main_clk_rate_hz = main_clock;
168 /* report if PLLA is more than mildly overclocked */
169 plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
171 #ifdef CONFIG_USB_ATMEL
173 * USB clock init: choose 48 MHz PLLB value,
174 * disable 48MHz clock during usb peripheral suspend.
176 * REVISIT: assumes MCK doesn't derive from PLLB!
178 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
179 AT91_PMC_PLLBR_USBDIV_2;
180 pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
184 * MCK and CPU derive from one of those primary clocks.
185 * For now, assume this parentage won't change.
187 mckr = readl(&pmc->mckr);
188 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
189 /* plla divisor by 2 */
190 plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
192 mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
195 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
196 #if defined(CONFIG_AT91RM9200)
198 mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
199 #elif defined(CONFIG_AT91SAM9G20)
200 /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
201 mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
202 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
203 if (mckr & AT91_PMC_MCKR_MDIV_MASK)
204 freq /= 2; /* processor clock division */
205 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
206 mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
207 (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
209 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
211 mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
213 cpu_clk_rate_hz = freq;