1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/armada100.h>
17 * Refer Section A.6 in Datasheet
19 struct armd1tmr_registers {
20 u32 clk_ctrl; /* Timer clk control reg */
21 u32 match[9]; /* Timer match registers */
22 u32 count[3]; /* Timer count registers */
25 u32 preload[3]; /* Timer preload value */
33 u32 cer; /* Timer count enable reg */
42 #define TIMER 0 /* Use TIMER 0 */
43 /* Each timer has 3 match registers */
44 #define MATCH_CMP(x) ((3 * TIMER) + x)
45 #define TIMER_LOAD_VAL 0xffffffff
46 #define COUNT_RD_REQ 0x1
48 DECLARE_GLOBAL_DATA_PTR;
49 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
51 /* For preventing risk of instability in reading counter value,
52 * first set read request to register cvwr and then read same
53 * register after it captures counter value.
55 ulong read_timer(void)
57 struct armd1tmr_registers *armd1timers =
58 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
59 volatile int loop=100;
61 writel(COUNT_RD_REQ, &armd1timers->cvwr);
63 return(readl(&armd1timers->cvwr));
66 static ulong get_timer_masked(void)
68 ulong now = read_timer();
70 if (now >= gd->arch.tbl) {
72 gd->arch.tbu += now - gd->arch.tbl;
74 /* we have an overflow ... */
75 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
82 ulong get_timer(ulong base)
84 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
88 void __udelay(unsigned long usec)
93 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
94 endtime = get_timer_masked() + delayticks;
96 while (get_timer_masked() < endtime);
104 struct armd1apb1_registers *apb1clkres =
105 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
106 struct armd1tmr_registers *armd1timers =
107 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
109 /* Enable Timer clock at 3.25 MHZ */
110 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
112 /* load value into timer */
113 writel(0x0, &armd1timers->clk_ctrl);
114 /* Use Timer 0 Match Resiger 0 */
115 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
116 /* Preload value is 0 */
117 writel(0x0, &armd1timers->preload[TIMER]);
118 /* Enable match comparator 0 for Timer 0 */
119 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
122 writel(0x1, &armd1timers->cer);
123 /* init the gd->arch.tbu and gd->arch.tbl value */
124 gd->arch.tbl = read_timer();
130 #define MPMU_APRR_WDTR (1<<4)
131 #define TMR_WFAR 0xbaba /* WDT Register First key */
132 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
135 * This function uses internal Watchdog Timer
136 * based reset mechanism.
137 * Steps to write watchdog registers (protected access)
138 * 1. Write key value to TMR_WFAR reg.
139 * 2. Write key value to TMP_WSAR reg.
140 * 3. Perform write operation.
142 void reset_cpu(unsigned long ignored)
144 struct armd1mpmu_registers *mpmu =
145 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
146 struct armd1tmr_registers *armd1timers =
147 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
150 /* negate hardware reset to the WDT after system reset */
151 val = readl(&mpmu->aprr);
152 val = val | MPMU_APRR_WDTR;
153 writel(val, &mpmu->aprr);
155 /* reset/enable WDT clock */
156 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
157 readl(&mpmu->wdtpcr);
158 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
159 readl(&mpmu->wdtpcr);
161 /* clear previous WDT status */
162 writel(TMR_WFAR, &armd1timers->wfar);
163 writel(TMP_WSAR, &armd1timers->wsar);
164 writel(0, &armd1timers->wdt_sts);
166 /* set match counter */
167 writel(TMR_WFAR, &armd1timers->wfar);
168 writel(TMP_WSAR, &armd1timers->wsar);
169 writel(0xf, &armd1timers->wdt_match_r);
171 /* enable WDT reset */
172 writel(TMR_WFAR, &armd1timers->wfar);
173 writel(TMP_WSAR, &armd1timers->wsar);
174 writel(0x3, &armd1timers->wdt_match_en);
180 * This function is derived from PowerPC code (read timebase as long long).
181 * On ARM it just returns the timer value.
183 unsigned long long get_ticks(void)
189 * This function is derived from PowerPC code (timebase clock frequency).
190 * On ARM it returns the number of timer ticks per second.
192 ulong get_tbclk(void)
194 return (ulong)CONFIG_SYS_HZ;