2 * armboot - Startup Code for ARM925 CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1510 from ARM920 code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm-offsets.h>
22 *************************************************************************
24 * Jump vector table as in table 3.1 in [1]
26 *************************************************************************
32 ldr pc, _undefined_instruction
33 ldr pc, _software_interrupt
34 ldr pc, _prefetch_abort
40 _undefined_instruction: .word undefined_instruction
41 _software_interrupt: .word software_interrupt
42 _prefetch_abort: .word prefetch_abort
43 _data_abort: .word data_abort
44 _not_used: .word not_used
48 .balignl 16,0xdeadbeef
52 *************************************************************************
54 * Startup Code (reset vector)
56 * do important init only if we don't start from memory!
57 * setup Memory and board specific bits prior to relocation.
58 * relocate armboot to ram
61 *************************************************************************
66 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
67 .word CONFIG_SPL_TEXT_BASE
69 .word CONFIG_SYS_TEXT_BASE
73 * These are defined in the board-specific linker script.
74 * Subtracting _start from them lets the linker put their
75 * relative position in the executable instead of leaving
80 .word __bss_start - _start
84 .word __bss_end - _start
91 /* IRQ stack memory (calculated at run-time) */
92 .globl IRQ_STACK_START
96 /* IRQ stack memory (calculated at run-time) */
97 .globl FIQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) + 8 bytes */
103 .globl IRQ_STACK_START_IN
108 * the actual reset code
113 * set the cpu to SVC32 mode
123 mov r1, #0x81 /* Set ARM925T configuration. */
124 mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
127 * turn off the watchdog, unlock/diable sequence
136 * mask all IRQs by setting all bits in the INTMR - default
139 ldr r0, =REG_IHL1_MIR
141 ldr r0, =REG_IHL2_MIR
145 * wait for dpll to lock
156 * we do sys-critical inits only at reboot,
157 * not when booting from ram!
159 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
165 /*------------------------------------------------------------------------------*/
167 .globl c_runtime_cpu_setup
173 *************************************************************************
175 * CPU_init_critical registers
177 * setup important registers
178 * setup memory timing
180 *************************************************************************
186 * flush v4 I/D caches
189 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
190 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
193 * disable MMU stuff and caches
195 mrc p15, 0, r0, c1, c0, 0
196 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
197 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
198 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
199 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
200 mcr p15, 0, r0, c1, c0, 0
203 * Go setup Memory and board specific bits prior to relocation.
205 mov ip, lr /* perserve link reg across call */
206 bl lowlevel_init /* go setup pll,mux,memory */
207 mov lr, ip /* restore link */
208 mov pc, lr /* back to my caller */
210 *************************************************************************
214 *************************************************************************
220 #define S_FRAME_SIZE 72
242 #define MODE_SVC 0x13
246 * use bad_save_user_regs for abort/prefetch/undef/swi ...
247 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
250 .macro bad_save_user_regs
251 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
252 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
254 ldr r2, IRQ_STACK_START_IN
255 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
256 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
260 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
261 mov r0, sp @ save current stack into r0 (param register)
264 .macro irq_save_user_regs
265 sub sp, sp, #S_FRAME_SIZE
266 stmia sp, {r0 - r12} @ Calling r0-r12
267 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
268 stmdb r8, {sp, lr}^ @ Calling SP, LR
269 str lr, [r8, #0] @ Save calling PC
271 str r6, [r8, #4] @ Save CPSR
272 str r0, [r8, #8] @ Save OLD_R0
276 .macro irq_restore_user_regs
277 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
279 ldr lr, [sp, #S_PC] @ Get PC
280 add sp, sp, #S_FRAME_SIZE
281 subs pc, lr, #4 @ return & move spsr_svc into cpsr
285 ldr r13, IRQ_STACK_START_IN
287 str lr, [r13] @ save caller lr in position 0 of saved stack
288 mrs lr, spsr @ get the spsr
289 str lr, [r13, #4] @ save spsr in position 1 of saved stack
291 mov r13, #MODE_SVC @ prepare SVC-Mode
293 msr spsr, r13 @ switch modes, make sure moves will execute
294 mov lr, pc @ capture return pc
295 movs pc, lr @ jump to next instruction & switch modes.
298 .macro get_irq_stack @ setup IRQ stack
299 ldr sp, IRQ_STACK_START
302 .macro get_fiq_stack @ setup FIQ stack
303 ldr sp, FIQ_STACK_START
310 undefined_instruction:
313 bl do_undefined_instruction
319 bl do_software_interrupt
339 #ifdef CONFIG_USE_IRQ
346 irq_restore_user_regs
351 /* someone ought to write a more effiction fiq_save_user_regs */
354 irq_restore_user_regs
375 ldr r1, rstctl1 /* get clkm1 reset ctl */
376 mov r3, #0x3 /* dsp_en + arm_rst = global reset */
377 strh r3, [r1] /* force reset */