1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for ARM920 CPU-core
5 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
6 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
10 #include <asm-offsets.h>
15 *************************************************************************
17 * Startup Code (called from the ARM reset exception vector)
19 * do important init only if we don't start from memory!
20 * relocate armboot to ram
22 * jump to second stage
24 *************************************************************************
31 * set the cpu to SVC32 mode
38 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
40 * relocate exception table
53 * we do sys-critical inits only at reboot,
54 * not when booting from ram!
56 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
62 /*------------------------------------------------------------------------------*/
64 .globl c_runtime_cpu_setup
70 *************************************************************************
72 * CPU_init_critical registers
74 * setup important registers
77 *************************************************************************
81 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
87 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
88 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
91 * disable MMU stuff and caches
93 mrc p15, 0, r0, c1, c0, 0
94 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
95 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
96 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
97 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
98 mcr p15, 0, r0, c1, c0, 0
100 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
102 * before relocating, we have to setup RAM timing
103 * because memory timing is board-dependend, you will
104 * find a lowlevel_init.S in your board directory.
112 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */