2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (called from the ARM reset exception vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) + 8 bytes */
102 .globl IRQ_STACK_START_IN
106 .globl _datarel_start
108 .word __datarel_start
110 .globl _datarelrolocal_start
111 _datarelrolocal_start:
112 .word __datarelrolocal_start
114 .globl _datarellocal_start
116 .word __datarellocal_start
118 .globl _datarelro_start
120 .word __datarelro_start
131 * the actual start code
136 * set the cpu to SVC32 mode
146 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
148 * relocate exception table
160 #ifdef CONFIG_S3C24X0
161 /* turn off the watchdog */
163 # if defined(CONFIG_S3C2400)
164 # define pWTCON 0x15300000
165 # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
166 # define CLKDIVN 0x14800014 /* clock divisor register */
168 # define pWTCON 0x53000000
169 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
170 # define INTSUBMSK 0x4A00001C
171 # define CLKDIVN 0x4C000014 /* clock divisor register */
179 * mask all IRQs by setting all bits in the INTMR - default
184 # if defined(CONFIG_S3C2410)
190 /* FCLK:HCLK:PCLK = 1:2:4 */
191 /* default FCLK is 120 MHz ! */
195 #endif /* CONFIG_S3C24X0 */
198 * we do sys-critical inits only at reboot,
199 * not when booting from ram!
201 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
205 /* Set stackpointer in internal RAM to call board_init_f */
207 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
211 /*------------------------------------------------------------------------------*/
214 * void relocate_code (addr_sp, gd, addr_moni)
216 * This "function" does not return, instead it continues in RAM
217 * after relocating the monitor code.
222 mov r4, r0 /* save addr_sp */
223 mov r5, r1 /* save addr of gd */
224 mov r6, r2 /* save addr of destination */
225 mov r7, r2 /* save addr of destination */
227 /* Set up the stack */
234 sub r2, r3, r2 /* r2 <- size of armboot */
235 add r2, r0, r2 /* r2 <- source end address */
240 ldmia r0!, {r9-r10} /* copy from source address [r0] */
241 stmia r6!, {r9-r10} /* copy to target address [r1] */
242 cmp r0, r2 /* until source end address [r2] */
245 #ifndef CONFIG_PRELOADER
246 /* fix got entries */
247 ldr r1, _TEXT_BASE /* Text base */
248 mov r0, r7 /* reloc addr */
249 ldr r2, _got_start /* addr in Flash */
250 ldr r3, _got_end /* addr in Flash */
267 #ifndef CONFIG_PRELOADER
270 ldr r3, _TEXT_BASE /* Text base */
271 mov r4, r7 /* reloc addr */
276 mov r2, #0x00000000 /* clear */
278 clbss_l:str r2, [r0] /* clear loop... */
288 * We are done. Do not return, instead branch to second part of board
289 * initialization, now running from RAM.
291 #ifdef CONFIG_NAND_SPL
294 _nand_boot: .word nand_boot
297 ldr r2, _board_init_r
299 add r2, r2, r7 /* position from board_init_r in RAM */
300 /* setup parameters for board_init_r */
301 mov r0, r5 /* gd_t */
302 mov r1, r7 /* dest_addr */
307 _board_init_r: .word board_init_r
311 *************************************************************************
313 * CPU_init_critical registers
315 * setup important registers
316 * setup memory timing
318 *************************************************************************
322 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
325 * flush v4 I/D caches
328 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
329 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
332 * disable MMU stuff and caches
334 mrc p15, 0, r0, c1, c0, 0
335 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
336 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
337 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
338 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
339 mcr p15, 0, r0, c1, c0, 0
342 * before relocating, we have to setup RAM timing
343 * because memory timing is board-dependend, you will
344 * find a lowlevel_init.S in your board directory.
352 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
355 *************************************************************************
359 *************************************************************************
365 #define S_FRAME_SIZE 72
387 #define MODE_SVC 0x13
391 * use bad_save_user_regs for abort/prefetch/undef/swi ...
392 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
395 .macro bad_save_user_regs
396 sub sp, sp, #S_FRAME_SIZE
397 stmia sp, {r0 - r12} @ Calling r0-r12
398 ldr r2, IRQ_STACK_START_IN
399 ldmia r2, {r2 - r3} @ get pc, cpsr
400 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
404 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
408 .macro irq_save_user_regs
409 sub sp, sp, #S_FRAME_SIZE
410 stmia sp, {r0 - r12} @ Calling r0-r12
412 stmdb r7, {sp, lr}^ @ Calling SP, LR
413 str lr, [r7, #0] @ Save calling PC
415 str r6, [r7, #4] @ Save CPSR
416 str r0, [r7, #8] @ Save OLD_R0
420 .macro irq_restore_user_regs
421 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
423 ldr lr, [sp, #S_PC] @ Get PC
424 add sp, sp, #S_FRAME_SIZE
425 /* return & move spsr_svc into cpsr */
430 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
432 str lr, [r13] @ save caller lr / spsr
436 mov r13, #MODE_SVC @ prepare SVC-Mode
443 .macro get_irq_stack @ setup IRQ stack
444 ldr sp, IRQ_STACK_START
447 .macro get_fiq_stack @ setup FIQ stack
448 ldr sp, FIQ_STACK_START
455 undefined_instruction:
458 bl do_undefined_instruction
464 bl do_software_interrupt
484 #ifdef CONFIG_USE_IRQ
491 irq_restore_user_regs
496 /* someone ought to write a more effiction fiq_save_user_regs */
499 irq_restore_user_regs