3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/s3c24x0_cpu.h>
38 int timer_load_val = 0;
39 static ulong timer_clk;
41 /* macro to read the 16 bit timer */
42 static inline ulong READ_TIMER(void)
44 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
46 return readl(&timers->tcnto4) & 0xffff;
49 static ulong timestamp;
54 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
57 /* use PWM Timer 4 because it has no output */
58 /* prescaler for Timer 4 is 16 */
59 writel(0x0f00, &timers->tcfg0);
60 if (timer_load_val == 0) {
62 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
63 * (default) and prescaler = 16. Should be 10390
64 * @33.25MHz and 15625 @ 50 MHz
66 timer_load_val = get_PCLK() / (2 * 16 * 100);
67 timer_clk = get_PCLK() / (2 * 16);
69 /* load value for 10 ms timeout */
70 lastdec = timer_load_val;
71 writel(timer_load_val, &timers->tcntb4);
72 /* auto load, manual update of timer 4 */
73 tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
74 writel(tmr, &timers->tcon);
75 /* auto load, start timer 4 */
76 tmr = (tmr & ~0x0700000) | 0x0500000;
77 writel(tmr, &timers->tcon);
84 * timer without interrupts
86 ulong get_timer(ulong base)
88 return get_timer_masked() - base;
91 void __udelay (unsigned long usec)
94 ulong start = get_ticks();
97 tmo *= (timer_load_val * 100);
100 while ((ulong) (get_ticks() - start) < tmo)
104 ulong get_timer_masked(void)
106 ulong tmr = get_ticks();
108 return tmr / (timer_clk / CONFIG_SYS_HZ);
111 void udelay_masked(unsigned long usec)
119 tmo *= (timer_load_val * 100);
122 tmo = usec * (timer_load_val * 100);
123 tmo /= (1000 * 1000);
126 endtime = get_ticks() + tmo;
129 ulong now = get_ticks();
130 diff = endtime - now;
135 * This function is derived from PowerPC code (read timebase as long long).
136 * On ARM it just returns the timer value.
138 unsigned long long get_ticks(void)
140 ulong now = READ_TIMER();
142 if (lastdec >= now) {
144 timestamp += lastdec - now;
146 /* we have an overflow ... */
147 timestamp += lastdec + timer_load_val - now;
155 * This function is derived from PowerPC code (timebase clock frequency).
156 * On ARM it returns the number of timer ticks per second.
158 ulong get_tbclk(void)
162 #if defined(CONFIG_SMDK2400)
163 tbclk = timer_load_val * 100;
164 #elif defined(CONFIG_SBC2410X) || \
165 defined(CONFIG_SMDK2410) || \
166 defined(CONFIG_S3C2440) || \
167 defined(CONFIG_VCMA9)
168 tbclk = CONFIG_SYS_HZ;
170 # error "tbclk not configured"
177 * reset the cpu by setting up the watchdog timer and let him time out
179 void reset_cpu(ulong ignored)
181 struct s3c24x0_watchdog *watchdog;
183 watchdog = s3c24x0_get_base_watchdog();
185 /* Disable watchdog */
186 writel(0x0000, &watchdog->wtcon);
188 /* Initialize watchdog timer count register */
189 writel(0x0001, &watchdog->wtcnt);
191 /* Enable watchdog timer; assert reset at timer timeout */
192 writel(0x0021, &watchdog->wtcon);
195 /* loop forever and wait for reset to happen */;
200 #endif /* CONFIG_S3C24X0 */