2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /* This code should work for both the S3C2400 and the S3C2410
28 * as they seem to have the same PLL and clock machinery inside.
29 * The different address mapping is handled by the s3c24xx.h files below.
36 #include <asm/arch/s3c24x0_cpu.h>
41 /* ------------------------------------------------------------------------- */
42 /* NOTE: This describes the proper use of this file.
44 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
46 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
47 * the specified bus in HZ.
49 /* ------------------------------------------------------------------------- */
51 static ulong get_PLLCLK(int pllreg)
53 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
57 r = readl(&clk_power->mpllcon);
58 else if (pllreg == UPLL)
59 r = readl(&clk_power->upllcon);
63 m = ((r & 0xFF000) >> 12) + 8;
64 p = ((r & 0x003F0) >> 4) + 2;
67 #if defined(CONFIG_S3C2440)
69 return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
71 return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
75 /* return FCLK frequency */
78 return get_PLLCLK(MPLL);
81 /* return HCLK frequency */
84 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
86 switch (readl(&clk_power->clkdivn) & 0x6) {
91 return get_FCLK() / 2;
93 return (readl(&clk_power->camdivn) & (1 << 9)) ?
94 get_FCLK() / 8 : get_FCLK() / 4;
96 return (readl(&clk_power->camdivn) & (1 << 8)) ?
97 get_FCLK() / 6 : get_FCLK() / 3;
100 return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
104 /* return PCLK frequency */
107 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
109 return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
112 /* return UCLK frequency */
115 return get_PLLCLK(UPLL);
118 #endif /* CONFIG_S3C24X0 */