3 * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
5 * SPDX-License-Identifier: GPL-2.0+
10 #if defined (CONFIG_IMX)
12 #include <asm/arch/imx-regs.h>
14 /* ------------------------------------------------------------------------- */
15 /* NOTE: This describes the proper use of this file.
17 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
18 * SH FIXME: 16780000 in our case
19 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
20 * the specified bus in HZ.
22 /* ------------------------------------------------------------------------- */
24 ulong get_systemPLLCLK(void)
26 /* FIXME: We assume System_SEL = 0 here */
28 u32 mfi = (spctl0 >> 10) & 0xf;
29 u32 mfn = spctl0 & 0x3f;
30 u32 mfd = (spctl0 >> 16) & 0x3f;
31 u32 pd = (spctl0 >> 26) & 0xf;
33 mfi = mfi<=5 ? 5 : mfi;
35 return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
38 ulong get_mcuPLLCLK(void)
40 /* FIXME: We assume System_SEL = 0 here */
42 u32 mfi = (mpctl0 >> 10) & 0xf;
43 u32 mfn = mpctl0 & 0x3f;
44 u32 mfd = (mpctl0 >> 16) & 0x3f;
45 u32 pd = (mpctl0 >> 26) & 0xf;
47 mfi = mfi<=5 ? 5 : mfi;
49 return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
54 return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
57 /* return HCLK frequency */
60 u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
61 printf("bclkdiv: %d\n", bclkdiv);
62 return get_systemPLLCLK() / bclkdiv;
65 /* return BCLK frequency */
71 ulong get_PERCLK1(void)
73 return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
76 ulong get_PERCLK2(void)
78 return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
81 ulong get_PERCLK3(void)
83 return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
86 #endif /* defined (CONFIG_IMX) */