2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the at91rm9200dk board by
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
35 * some parameters for the board
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL
41 #include <asm/arch/AT91RM9200.h>
46 .word TEXT_BASE-PHYS_FLASH_1
53 /* Get the CKGR Base Address */
54 ldr r1, =AT91C_BASE_CKGR
55 /* Main oscillator Enable register */
56 #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
57 ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
59 ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
61 str r0, [r1, #AT91C_CKGR_MOR]
62 /* Add loop to compensate Main Oscillator startup time */
68 /* memory control configuration */
69 /* this isn't very elegant, but what the heck */
82 /* delay - this is all done by guess */
84 /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
101 /* switch from FastBus to Asynchronous clock mode */
102 mrc p15, 0, r0, c1, c0, 0
103 orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF)
104 mcr p15, 0, r0, c1, c0, 0
106 /* everything is fine now */
113 .word CONFIG_SYS_EBI_CFGR_VAL
115 .word CONFIG_SYS_SMC_CSR0_VAL
117 .word CONFIG_SYS_PLLAR_VAL
119 .word CONFIG_SYS_PLLBR_VAL
121 .word CONFIG_SYS_MCKR_VAL
122 /* here there's a delay */
125 .word CONFIG_SYS_PIOC_ASR_VAL
127 .word CONFIG_SYS_PIOC_BSR_VAL
129 .word CONFIG_SYS_PIOC_PDR_VAL
131 .word CONFIG_SYS_EBI_CSA_VAL
133 .word CONFIG_SYS_SDRC_CR_VAL
135 .word CONFIG_SYS_SDRC_MR_VAL
136 .word CONFIG_SYS_SDRAM
137 .word CONFIG_SYS_SDRAM_VAL
139 .word CONFIG_SYS_SDRC_MR_VAL1
140 .word CONFIG_SYS_SDRAM
141 .word CONFIG_SYS_SDRAM_VAL
142 .word CONFIG_SYS_SDRAM
143 .word CONFIG_SYS_SDRAM_VAL
144 .word CONFIG_SYS_SDRAM
145 .word CONFIG_SYS_SDRAM_VAL
146 .word CONFIG_SYS_SDRAM
147 .word CONFIG_SYS_SDRAM_VAL
148 .word CONFIG_SYS_SDRAM
149 .word CONFIG_SYS_SDRAM_VAL
150 .word CONFIG_SYS_SDRAM
151 .word CONFIG_SYS_SDRAM_VAL
152 .word CONFIG_SYS_SDRAM
153 .word CONFIG_SYS_SDRAM_VAL
154 .word CONFIG_SYS_SDRAM
155 .word CONFIG_SYS_SDRAM_VAL
157 .word CONFIG_SYS_SDRC_MR_VAL2
158 .word CONFIG_SYS_SDRAM1
159 .word CONFIG_SYS_SDRAM_VAL
161 .word CONFIG_SYS_SDRC_TR_VAL
162 .word CONFIG_SYS_SDRAM
163 .word CONFIG_SYS_SDRAM_VAL
165 .word CONFIG_SYS_SDRC_MR_VAL3
166 .word CONFIG_SYS_SDRAM
167 .word CONFIG_SYS_SDRAM_VAL
168 /* SMRDATA1 is 176 bytes long */
169 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */