3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
26 #ifdef CONFIG_DRIVER_ETHER
29 #if defined(CONFIG_CMD_NET)
33 * dm9161_IsPhyConnected
35 * Reads the 2 PHY ID registers
37 * p_mac - pointer to AT91S_EMAC struct
39 * TRUE - if id read successfully
42 unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
44 unsigned short Id1, Id2;
46 at91rm9200_EmacEnableMDIO (p_mac);
47 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
48 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
49 at91rm9200_EmacDisableMDIO (p_mac);
51 if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
52 ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
62 * Link parallel detection status of MAC is checked and set in the
63 * MAC configuration registers
65 * p_mac - pointer to MAC
67 * TRUE - if link status set succesfully
68 * FALSE - if link status not set
70 UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
72 unsigned short stat1, stat2;
74 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
77 if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
80 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
83 if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
84 /*set Emac for 100BaseTX and Full Duplex */
85 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
89 if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
90 /*set MII for 10BaseT and Full Duplex */
91 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
92 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
97 if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
98 /*set MII for 100BaseTX and Half Duplex */
99 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
100 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
105 if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
106 /*set MII for 10BaseT and Half Duplex */
107 p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
118 * MAC starts checking its link by using parallel detection and
119 * Autonegotiation and the same is set in the MAC configuration registers
121 * p_mac - pointer to struct AT91S_EMAC
123 * TRUE - if link status set succesfully
124 * FALSE - if link status not set
126 UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
129 unsigned short IntValue;
131 at91rm9200_EmacEnableMDIO (p_mac);
133 if (!dm9161_GetLinkSpeed (p_mac)) {
134 /* Try another time */
135 ret = dm9161_GetLinkSpeed (p_mac);
138 /* Disable PHY Interrupts */
139 at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
140 /* set FDX, SPD, Link, INTR masks */
141 IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
142 DM9161_LINK_MASK | DM9161_INTR_MASK);
143 at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
144 at91rm9200_EmacDisableMDIO (p_mac);
152 * dm9161_AutoNegotiate
154 * MAC Autonegotiates with the partner status of same is set in the
155 * MAC configuration registers
157 * dev - pointer to struct net_device
159 * TRUE - if link status set successfully
160 * FALSE - if link status not set
162 UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
164 unsigned short value;
165 unsigned short PhyAnar;
166 unsigned short PhyAnalpar;
168 /* Set dm9161 control register */
169 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
171 value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
172 value |= DM9161_ISOLATE; /* Electrically isolate PHY */
173 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
176 /* Set the Auto_negotiation Advertisement Register */
177 /* MII advertising for Next page, 100BaseTxFD and HD, */
178 /* 10BaseTFD and HD, IEEE 802.3 */
179 PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
180 DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
181 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
184 /* Read the Control Register */
185 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
188 value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
189 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
191 /* Restart Auto_negotiation */
192 value |= DM9161_RESTART_AUTONEG;
193 value &= ~DM9161_ISOLATE;
194 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
197 /*check AutoNegotiate complete */
199 at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
200 if (!(value & DM9161_AUTONEG_COMP))
203 /* Get the AutoNeg Link partner base page */
204 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
207 if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
208 /*set MII for 100BaseTX and Full Duplex */
209 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
213 if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
214 /*set MII for 10BaseT and Full Duplex */
215 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
216 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
225 #endif /* CONFIG_DRIVER_ETHER */