2 * TNETV107X: Watchdog timer implementation (for reset)
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/arch/clock.h>
26 #define MAX_DIV 0xFFFE0001
30 #define KICK_LOCK_1 0x5555
31 #define KICK_LOCK_2 0xaaaa
35 #define CHANGE_LOCK_1 0x6666
36 #define CHANGE_LOCK_2 0xbbbb
40 #define DISABLE_LOCK_1 0x7777
41 #define DISABLE_LOCK_2 0xcccc
42 #define DISABLE_LOCK_3 0xdddd
46 #define PRESCALE_LOCK_1 0x5a5a
47 #define PRESCALE_LOCK_2 0xa5a5
51 static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
53 #define wdt_reg_read(reg) __raw_readl(®s->reg)
54 #define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
56 static int write_prescale_reg(unsigned long prescale_value)
58 wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
59 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
62 wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
63 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
66 wdt_reg_write(prescale, prescale_value);
71 static int write_change_reg(unsigned long initial_timer_value)
73 wdt_reg_write(change_lock, CHANGE_LOCK_1);
74 if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
77 wdt_reg_write(change_lock, CHANGE_LOCK_2);
78 if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
81 wdt_reg_write(change, initial_timer_value);
86 static int wdt_control(unsigned long disable_value)
88 wdt_reg_write(disable_lock, DISABLE_LOCK_1);
89 if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
92 wdt_reg_write(disable_lock, DISABLE_LOCK_2);
93 if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
96 wdt_reg_write(disable_lock, DISABLE_LOCK_3);
97 if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
100 wdt_reg_write(disable, disable_value);
104 static int wdt_set_period(unsigned long msec)
106 unsigned long change_value, count_value;
107 unsigned long prescale_value = 1;
108 unsigned long refclk_khz, maxdiv;
111 refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
112 maxdiv = (MAX_DIV / refclk_khz);
114 if ((!msec) || (msec > maxdiv))
117 count_value = refclk_khz * msec;
118 if (count_value > 0xffff) {
119 change_value = count_value / 0xffff + 1;
120 prescale_value = count_value / change_value;
122 change_value = count_value;
125 ret = write_prescale_reg(prescale_value - 1);
129 ret = write_change_reg(change_value);
136 unsigned long last_wdt = -1;
138 int wdt_start(unsigned long msecs)
141 ret = wdt_control(0);
144 ret = wdt_set_period(msecs);
147 ret = wdt_control(1);
158 return wdt_control(0);
163 wdt_reg_write(kick_lock, KICK_LOCK_1);
164 if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
167 wdt_reg_write(kick_lock, KICK_LOCK_2);
168 if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
171 wdt_reg_write(kick, 1);
175 void reset_cpu(ulong addr)
177 clk_enable(TNETV107X_LPSC_WDT_ARM);