2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
36 #ifdef CONFIG_ENABLE_MMU
37 #include <asm/proc/domain.h>
40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
41 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
45 *************************************************************************
47 * Jump vector table as in table 3.1 in [1]
49 *************************************************************************
54 #ifndef CONFIG_NAND_SPL
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction:
64 .word undefined_instruction
66 .word software_interrupt
78 .word 0x12345678 /* now 16*4=64 */
85 .balignl 16,0xdeadbeef
87 *************************************************************************
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * setup Memory and board specific bits prior to relocation.
93 * relocate armboot to ram
96 *************************************************************************
101 .word CONFIG_SYS_TEXT_BASE
104 * Below variable is very important because we use MMU in U-Boot.
105 * Without it, we cannot run code correctly before MMU is ON.
109 .word CONFIG_SYS_PHY_UBOOT_BASE
112 * These are defined in the board-specific linker script.
113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
118 .globl _bss_start_ofs
120 .word __bss_start - _start
126 .globl _datarel_start_ofs
128 .word __datarel_start - _start
130 .globl _datarelrolocal_start_ofs
131 _datarelrolocal_start_ofs:
132 .word __datarelrolocal_start - _start
134 .globl _datarellocal_start_ofs
135 _datarellocal_start_ofs:
136 .word __datarellocal_start - _start
138 .globl _datarelro_start_ofs
139 _datarelro_start_ofs:
140 .word __datarelro_start - _start
142 .globl _rel_dyn_start_ofs
144 .word __rel_dyn_start - _start
146 .globl _rel_dyn_end_ofs
148 .word __rel_dyn_end - _start
150 .globl _dynsym_start_ofs
152 .word __dynsym_start - _start
154 /* IRQ stack memory (calculated at run-time) + 8 bytes */
155 .globl IRQ_STACK_START_IN
160 * the actual reset code
165 * set the cpu to SVC32 mode
173 *************************************************************************
175 * CPU_init_critical registers
177 * setup important registers
178 * setup memory timing
180 *************************************************************************
183 * we do sys-critical inits only at reboot,
184 * not when booting from ram!
188 * When booting from NAND - it has definitely been a reset, so, no need
189 * to flush caches and disable the MMU
191 #ifndef CONFIG_NAND_SPL
193 * flush v4 I/D caches
196 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
197 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
200 * disable MMU stuff and caches
202 mrc p15, 0, r0, c1, c0, 0
203 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
204 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
205 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
206 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
208 /* Prepare to disable the MMU */
209 adr r2, mmu_disable_phys
210 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
214 /* Run in a single cache-line */
216 mcr p15, 0, r0, c1, c0, 0
222 #ifdef CONFIG_DISABLE_TCM
226 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
232 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
234 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
239 #ifdef CONFIG_PERIPORT_REMAP
240 /* Peri port setup */
241 ldr r0, =CONFIG_PERIPORT_BASE
242 orr r0, r0, #CONFIG_PERIPORT_SIZE
243 mcr p15,0,r0,c15,c2,4
247 * Go setup Memory and board specific bits prior to relocation.
249 bl lowlevel_init /* go setup pll,mux,memory */
251 /* Set stackpointer in internal RAM to call board_init_f */
253 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
257 /*------------------------------------------------------------------------------*/
260 * void relocate_code (addr_sp, gd, addr_moni)
262 * This "function" does not return, instead it continues in RAM
263 * after relocating the monitor code.
268 mov r4, r0 /* save addr_sp */
269 mov r5, r1 /* save addr of gd */
270 mov r6, r2 /* save addr of destination */
271 mov r7, r2 /* save addr of destination */
273 /* Set up the stack */
279 ldr r3, _bss_start_ofs
280 add r2, r0, r3 /* r2 <- source end address */
284 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
286 ldmia r0!, {r9-r10} /* copy from source address [r0] */
287 stmia r6!, {r9-r10} /* copy to target address [r1] */
288 cmp r0, r2 /* until source end address [r2] */
291 #ifndef CONFIG_PRELOADER
293 * fix .rel.dyn relocations
295 ldr r0, _TEXT_BASE /* r0 <- Text base */
296 sub r9, r7, r0 /* r9 <- relocation offset */
297 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
298 add r10, r10, r0 /* r10 <- sym table in FLASH */
299 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
300 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
301 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
302 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
304 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
305 add r0, r0, r9 /* r0 <- location to fix up in RAM */
308 cmp r8, #23 /* relative fixup? */
310 cmp r8, #2 /* absolute fixup? */
312 /* ignore unknown type of fixup */
315 /* absolute fix: set location to (offset) symbol value */
316 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
317 add r1, r10, r1 /* r1 <- address of symbol in table */
318 ldr r1, [r1, #4] /* r1 <- symbol value */
319 add r1, r1, r9 /* r1 <- relocated sym addr */
322 /* relative fix: increase location by offset */
327 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
331 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
333 #ifdef CONFIG_ENABLE_MMU
335 /* enable domain access */
337 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
339 /* Set the TTB register */
340 ldr r0, _mmu_table_base
341 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
345 mcr p15, 0, r1, c2, c0, 0
348 mrc p15, 0, r0, c1, c0, 0
349 orr r0, r0, #1 /* Set CR_M to enable MMU */
351 /* Prepare to enable the MMU */
361 /* Run in a single cache-line */
364 mcr p15, 0, r0, c1, c0, 0
372 #ifndef CONFIG_PRELOADER
373 ldr r0, _bss_start_ofs
375 ldr r3, _TEXT_BASE /* Text base */
376 mov r4, r7 /* reloc addr */
379 mov r2, #0x00000000 /* clear */
381 clbss_l:str r2, [r0] /* clear loop... */
391 * We are done. Do not return, instead branch to second part of board
392 * initialization, now running from RAM.
394 #ifdef CONFIG_NAND_SPL
397 _nand_boot: .word nand_boot
399 ldr r0, _board_init_r_ofs
402 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
405 /* setup parameters for board_init_r */
406 mov r0, r5 /* gd_t */
407 mov r1, r7 /* dest_addr */
412 .word board_init_r - _start
415 #ifdef CONFIG_ENABLE_MMU
420 #ifndef CONFIG_NAND_SPL
422 * we assume that cache operation is done before. (eg. cleanup_before_linux())
423 * actually, we don't need to do anything about cache if not use d-cache in
424 * U-Boot. So, in this function we clean only MMU. by scsuh
426 * void theLastJump(void *kernel, int arch_num, uint boot_params);
428 #ifdef CONFIG_ENABLE_MMU
433 ldr r4, _TEXT_PHY_BASE
434 adr r5, phy_last_jump
442 mrc p15, 0, r0, c1, c0, 0
443 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
444 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
445 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
446 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
447 mcr p15, 0, r0, c1, c0, 0
449 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
457 *************************************************************************
461 *************************************************************************
466 #define S_FRAME_SIZE 72
488 #define MODE_SVC 0x13
492 * use bad_save_user_regs for abort/prefetch/undef/swi ...
495 .macro bad_save_user_regs
496 /* carve out a frame on current user stack */
497 sub sp, sp, #S_FRAME_SIZE
498 /* Save user registers (now in svc mode) r0-r12 */
501 ldr r2, IRQ_STACK_START_IN
502 /* get values for "aborted" pc and cpsr (into parm regs) */
504 /* grab pointer to old stack */
505 add r0, sp, #S_FRAME_SIZE
509 /* save sp_SVC, lr_SVC, pc, cpsr */
511 /* save current stack into r0 (param register) */
516 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
518 /* save caller lr in position 0 of saved stack */
522 /* save spsr in position 1 of saved stack */
525 /* prepare SVC-Mode */
528 /* switch modes, make sure moves will execute */
530 /* capture return pc */
532 /* jump to next instruction & switch modes. */
536 .macro get_bad_stack_swi
537 /* space on current stack for scratch reg. */
539 /* save R0's value. */
541 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
542 /* save caller lr in position 0 of saved stack */
546 /* save spsr in position 1 of saved stack */
550 /* pop stack entry */
558 undefined_instruction:
561 bl do_undefined_instruction
567 bl do_software_interrupt
598 #endif /* CONFIG_NAND_SPL */