2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
36 #ifdef CONFIG_ENABLE_MMU
37 #include <asm/proc/domain.h>
40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
41 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
45 *************************************************************************
47 * Jump vector table as in table 3.1 in [1]
49 *************************************************************************
54 #ifndef CONFIG_NAND_SPL
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction:
64 .word undefined_instruction
66 .word software_interrupt
78 .word 0x12345678 /* now 16*4=64 */
85 .balignl 16,0xdeadbeef
87 *************************************************************************
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * setup Memory and board specific bits prior to relocation.
93 * relocate armboot to ram
96 *************************************************************************
101 .word CONFIG_SYS_TEXT_BASE
104 * Below variable is very important because we use MMU in U-Boot.
105 * Without it, we cannot run code correctly before MMU is ON.
109 .word CONFIG_SYS_PHY_UBOOT_BASE
111 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
112 .globl _armboot_start
118 * These are defined in the board-specific linker script.
128 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
129 /* IRQ stack memory (calculated at run-time) + 8 bytes */
130 .globl IRQ_STACK_START_IN
134 .globl _datarel_start
136 .word __datarel_start
138 .globl _datarelrolocal_start
139 _datarelrolocal_start:
140 .word __datarelrolocal_start
142 .globl _datarellocal_start
144 .word __datarellocal_start
146 .globl _datarelro_start
148 .word __datarelro_start
159 * the actual reset code
164 * set the cpu to SVC32 mode
172 *************************************************************************
174 * CPU_init_critical registers
176 * setup important registers
177 * setup memory timing
179 *************************************************************************
182 * we do sys-critical inits only at reboot,
183 * not when booting from ram!
187 * When booting from NAND - it has definitely been a reset, so, no need
188 * to flush caches and disable the MMU
190 #ifndef CONFIG_NAND_SPL
192 * flush v4 I/D caches
195 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
196 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
199 * disable MMU stuff and caches
201 mrc p15, 0, r0, c1, c0, 0
202 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
203 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
204 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
205 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
207 /* Prepare to disable the MMU */
208 adr r2, mmu_disable_phys
209 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
213 /* Run in a single cache-line */
215 mcr p15, 0, r0, c1, c0, 0
221 #ifdef CONFIG_DISABLE_TCM
225 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
231 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
233 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
238 #ifdef CONFIG_PERIPORT_REMAP
239 /* Peri port setup */
240 ldr r0, =CONFIG_PERIPORT_BASE
241 orr r0, r0, #CONFIG_PERIPORT_SIZE
242 mcr p15,0,r0,c15,c2,4
246 * Go setup Memory and board specific bits prior to relocation.
248 bl lowlevel_init /* go setup pll,mux,memory */
250 /* Set stackpointer in internal RAM to call board_init_f */
252 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
256 /*------------------------------------------------------------------------------*/
259 * void relocate_code (addr_sp, gd, addr_moni)
261 * This "function" does not return, instead it continues in RAM
262 * after relocating the monitor code.
267 mov r4, r0 /* save addr_sp */
268 mov r5, r1 /* save addr of gd */
269 mov r6, r2 /* save addr of destination */
270 mov r7, r2 /* save addr of destination */
272 /* Set up the stack */
279 sub r2, r3, r2 /* r2 <- size of armboot */
280 add r2, r0, r2 /* r2 <- source end address */
284 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
286 ldmia r0!, {r9-r10} /* copy from source address [r0] */
287 stmia r6!, {r9-r10} /* copy to target address [r1] */
288 cmp r0, r2 /* until source end address [r2] */
291 #ifndef CONFIG_PRELOADER
292 /* fix got entries */
293 ldr r1, _TEXT_BASE /* Text base */
294 mov r0, r7 /* reloc addr */
295 ldr r2, _got_start /* addr in Flash */
296 ldr r3, _got_end /* addr in Flash */
311 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
313 #ifdef CONFIG_ENABLE_MMU
315 /* enable domain access */
317 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
319 /* Set the TTB register */
320 ldr r0, _mmu_table_base
321 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
325 mcr p15, 0, r1, c2, c0, 0
328 mrc p15, 0, r0, c1, c0, 0
329 orr r0, r0, #1 /* Set CR_M to enable MMU */
331 /* Prepare to enable the MMU */
341 /* Run in a single cache-line */
344 mcr p15, 0, r0, c1, c0, 0
352 #ifndef CONFIG_PRELOADER
355 ldr r3, _TEXT_BASE /* Text base */
356 mov r4, r7 /* reloc addr */
361 mov r2, #0x00000000 /* clear */
363 clbss_l:str r2, [r0] /* clear loop... */
373 * We are done. Do not return, instead branch to second part of board
374 * initialization, now running from RAM.
376 #ifdef CONFIG_NAND_SPL
379 _nand_boot: .word nand_boot
382 ldr r2, _board_init_r
384 add r2, r2, r7 /* position from board_init_r in RAM */
385 /* setup parameters for board_init_r */
386 mov r0, r5 /* gd_t */
387 mov r1, r7 /* dest_addr */
392 _board_init_r: .word board_init_r
395 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
398 * the actual reset code
403 * set the cpu to SVC32 mode
411 *************************************************************************
413 * CPU_init_critical registers
415 * setup important registers
416 * setup memory timing
418 *************************************************************************
421 * we do sys-critical inits only at reboot,
422 * not when booting from ram!
426 * When booting from NAND - it has definitely been a reset, so, no need
427 * to flush caches and disable the MMU
429 #ifndef CONFIG_NAND_SPL
431 * flush v4 I/D caches
434 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
435 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
438 * disable MMU stuff and caches
440 mrc p15, 0, r0, c1, c0, 0
441 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
442 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
443 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
444 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
446 /* Prepare to disable the MMU */
447 adr r2, mmu_disable_phys
448 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
452 /* Run in a single cache-line */
454 mcr p15, 0, r0, c1, c0, 0
460 #ifdef CONFIG_DISABLE_TCM
464 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
470 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
472 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
477 #ifdef CONFIG_PERIPORT_REMAP
478 /* Peri port setup */
479 ldr r0, =CONFIG_PERIPORT_BASE
480 orr r0, r0, #CONFIG_PERIPORT_SIZE
481 mcr p15,0,r0,c15,c2,4
485 * Go setup Memory and board specific bits prior to relocation.
487 bl lowlevel_init /* go setup pll,mux,memory */
489 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
490 relocate: /* relocate U-Boot to RAM */
491 adr r0, _start /* r0 <- current position of code */
492 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
493 cmp r0, r1 /* don't reloc during debug */
496 ldr r2, _armboot_start
498 sub r2, r3, r2 /* r2 <- size of armboot */
499 add r2, r0, r2 /* r2 <- source end address */
502 ldmia r0!, {r3-r10} /* copy from source address [r0] */
503 stmia r1!, {r3-r10} /* copy to target address [r1] */
504 cmp r0, r2 /* until source end address [r2] */
506 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
508 #ifdef CONFIG_ENABLE_MMU
510 /* enable domain access */
512 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
514 /* Set the TTB register */
515 ldr r0, _mmu_table_base
516 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
520 mcr p15, 0, r1, c2, c0, 0
523 mrc p15, 0, r0, c1, c0, 0
524 orr r0, r0, #1 /* Set CR_M to enable MMU */
526 /* Prepare to enable the MMU */
536 /* Run in a single cache-line */
539 mcr p15, 0, r0, c1, c0, 0
546 /* Set up the stack */
548 ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
549 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
550 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
551 sub sp, r0, #12 /* leave 3 words for abort-stack */
552 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
555 ldr r0, _bss_start /* find start of bss segment */
556 ldr r1, _bss_end /* stop here */
557 mov r2, #0 /* clear */
560 str r2, [r0] /* clear loop... */
565 #ifndef CONFIG_NAND_SPL
566 ldr pc, _start_armboot
575 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
577 #ifdef CONFIG_ENABLE_MMU
582 #ifndef CONFIG_NAND_SPL
584 * we assume that cache operation is done before. (eg. cleanup_before_linux())
585 * actually, we don't need to do anything about cache if not use d-cache in
586 * U-Boot. So, in this function we clean only MMU. by scsuh
588 * void theLastJump(void *kernel, int arch_num, uint boot_params);
590 #ifdef CONFIG_ENABLE_MMU
595 ldr r4, _TEXT_PHY_BASE
596 adr r5, phy_last_jump
604 mrc p15, 0, r0, c1, c0, 0
605 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
606 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
607 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
608 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
609 mcr p15, 0, r0, c1, c0, 0
611 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
619 *************************************************************************
623 *************************************************************************
628 #define S_FRAME_SIZE 72
650 #define MODE_SVC 0x13
654 * use bad_save_user_regs for abort/prefetch/undef/swi ...
657 .macro bad_save_user_regs
658 /* carve out a frame on current user stack */
659 sub sp, sp, #S_FRAME_SIZE
660 /* Save user registers (now in svc mode) r0-r12 */
663 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
664 ldr r2, _armboot_start
665 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
666 /* set base 2 words into abort stack */
667 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8)
669 ldr r2, IRQ_STACK_START_IN
671 /* get values for "aborted" pc and cpsr (into parm regs) */
673 /* grab pointer to old stack */
674 add r0, sp, #S_FRAME_SIZE
678 /* save sp_SVC, lr_SVC, pc, cpsr */
680 /* save current stack into r0 (param register) */
685 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
686 /* setup our mode stack (enter in banked mode) */
687 ldr r13, _armboot_start
688 /* move past malloc pool */
689 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
690 /* move to reserved a couple spots for abort stack */
691 sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8)
693 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
696 /* save caller lr in position 0 of saved stack */
700 /* save spsr in position 1 of saved stack */
703 /* prepare SVC-Mode */
706 /* switch modes, make sure moves will execute */
708 /* capture return pc */
710 /* jump to next instruction & switch modes. */
714 .macro get_bad_stack_swi
715 /* space on current stack for scratch reg. */
717 /* save R0's value. */
719 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
720 /* get data regions start */
721 ldr r0, _armboot_start
722 /* move past malloc pool */
723 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
724 /* move past gbl and a couple spots for abort stack */
725 sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8)
727 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
729 /* save caller lr in position 0 of saved stack */
733 /* save spsr in position 1 of saved stack */
737 /* pop stack entry */
745 undefined_instruction:
748 bl do_undefined_instruction
754 bl do_software_interrupt
785 #endif /* CONFIG_NAND_SPL */