2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
36 #ifdef CONFIG_ENABLE_MMU
37 #include <asm/proc/domain.h>
40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
41 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
45 *************************************************************************
47 * Jump vector table as in table 3.1 in [1]
49 *************************************************************************
54 #ifndef CONFIG_NAND_SPL
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction:
64 .word undefined_instruction
66 .word software_interrupt
78 .word 0x12345678 /* now 16*4=64 */
85 .balignl 16,0xdeadbeef
87 *************************************************************************
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * setup Memory and board specific bits prior to relocation.
93 * relocate armboot to ram
96 *************************************************************************
101 .word CONFIG_SYS_TEXT_BASE
104 * Below variable is very important because we use MMU in U-Boot.
105 * Without it, we cannot run code correctly before MMU is ON.
109 .word CONFIG_SYS_PHY_UBOOT_BASE
111 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
112 .globl _armboot_start
118 * These are defined in the board-specific linker script.
119 * Subtracting _start from them lets the linker put their
120 * relative position in the executable instead of leaving
124 .globl _bss_start_ofs
126 .word __bss_start - _start
132 .globl _datarel_start_ofs
134 .word __datarel_start - _start
136 .globl _datarelrolocal_start_ofs
137 _datarelrolocal_start_ofs:
138 .word __datarelrolocal_start - _start
140 .globl _datarellocal_start_ofs
141 _datarellocal_start_ofs:
142 .word __datarellocal_start - _start
144 .globl _datarelro_start_ofs
145 _datarelro_start_ofs:
146 .word __datarelro_start - _start
148 .globl _rel_dyn_start_ofs
150 .word __rel_dyn_start - _start
152 .globl _rel_dyn_end_ofs
154 .word __rel_dyn_end - _start
156 .globl _dynsym_start_ofs
158 .word __dynsym_start - _start
160 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
161 /* IRQ stack memory (calculated at run-time) + 8 bytes */
162 .globl IRQ_STACK_START_IN
167 * the actual reset code
172 * set the cpu to SVC32 mode
180 *************************************************************************
182 * CPU_init_critical registers
184 * setup important registers
185 * setup memory timing
187 *************************************************************************
190 * we do sys-critical inits only at reboot,
191 * not when booting from ram!
195 * When booting from NAND - it has definitely been a reset, so, no need
196 * to flush caches and disable the MMU
198 #ifndef CONFIG_NAND_SPL
200 * flush v4 I/D caches
203 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
204 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
207 * disable MMU stuff and caches
209 mrc p15, 0, r0, c1, c0, 0
210 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
211 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
212 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
213 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
215 /* Prepare to disable the MMU */
216 adr r2, mmu_disable_phys
217 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
221 /* Run in a single cache-line */
223 mcr p15, 0, r0, c1, c0, 0
229 #ifdef CONFIG_DISABLE_TCM
233 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
239 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
241 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
246 #ifdef CONFIG_PERIPORT_REMAP
247 /* Peri port setup */
248 ldr r0, =CONFIG_PERIPORT_BASE
249 orr r0, r0, #CONFIG_PERIPORT_SIZE
250 mcr p15,0,r0,c15,c2,4
254 * Go setup Memory and board specific bits prior to relocation.
256 bl lowlevel_init /* go setup pll,mux,memory */
258 /* Set stackpointer in internal RAM to call board_init_f */
260 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
264 /*------------------------------------------------------------------------------*/
267 * void relocate_code (addr_sp, gd, addr_moni)
269 * This "function" does not return, instead it continues in RAM
270 * after relocating the monitor code.
275 mov r4, r0 /* save addr_sp */
276 mov r5, r1 /* save addr of gd */
277 mov r6, r2 /* save addr of destination */
278 mov r7, r2 /* save addr of destination */
280 /* Set up the stack */
286 ldr r3, _bss_start_ofs
287 add r2, r0, r3 /* r2 <- source end address */
291 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
293 ldmia r0!, {r9-r10} /* copy from source address [r0] */
294 stmia r6!, {r9-r10} /* copy to target address [r1] */
295 cmp r0, r2 /* until source end address [r2] */
298 #ifndef CONFIG_PRELOADER
300 * fix .rel.dyn relocations
302 ldr r0, _TEXT_BASE /* r0 <- Text base */
303 sub r9, r7, r0 /* r9 <- relocation offset */
304 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
305 add r10, r10, r0 /* r10 <- sym table in FLASH */
306 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
307 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
308 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
309 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
311 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
312 add r0, r0, r9 /* r0 <- location to fix up in RAM */
315 cmp r8, #23 /* relative fixup? */
317 cmp r8, #2 /* absolute fixup? */
319 /* ignore unknown type of fixup */
322 /* absolute fix: set location to (offset) symbol value */
323 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
324 add r1, r10, r1 /* r1 <- address of symbol in table */
325 ldr r1, [r1, #4] /* r1 <- symbol value */
326 add r1, r1, r9 /* r1 <- relocated sym addr */
329 /* relative fix: increase location by offset */
334 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
338 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
340 #ifdef CONFIG_ENABLE_MMU
342 /* enable domain access */
344 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
346 /* Set the TTB register */
347 ldr r0, _mmu_table_base
348 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
352 mcr p15, 0, r1, c2, c0, 0
355 mrc p15, 0, r0, c1, c0, 0
356 orr r0, r0, #1 /* Set CR_M to enable MMU */
358 /* Prepare to enable the MMU */
368 /* Run in a single cache-line */
371 mcr p15, 0, r0, c1, c0, 0
379 #ifndef CONFIG_PRELOADER
380 ldr r0, _bss_start_ofs
382 ldr r3, _TEXT_BASE /* Text base */
383 mov r4, r7 /* reloc addr */
386 mov r2, #0x00000000 /* clear */
388 clbss_l:str r2, [r0] /* clear loop... */
398 * We are done. Do not return, instead branch to second part of board
399 * initialization, now running from RAM.
401 #ifdef CONFIG_NAND_SPL
404 _nand_boot: .word nand_boot
406 ldr r0, _board_init_r_ofs
409 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
412 /* setup parameters for board_init_r */
413 mov r0, r5 /* gd_t */
414 mov r1, r7 /* dest_addr */
419 .word board_init_r - _start
422 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
425 * the actual reset code
430 * set the cpu to SVC32 mode
438 *************************************************************************
440 * CPU_init_critical registers
442 * setup important registers
443 * setup memory timing
445 *************************************************************************
448 * we do sys-critical inits only at reboot,
449 * not when booting from ram!
453 * When booting from NAND - it has definitely been a reset, so, no need
454 * to flush caches and disable the MMU
456 #ifndef CONFIG_NAND_SPL
458 * flush v4 I/D caches
461 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
462 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
465 * disable MMU stuff and caches
467 mrc p15, 0, r0, c1, c0, 0
468 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
469 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
470 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
471 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
473 /* Prepare to disable the MMU */
474 adr r2, mmu_disable_phys
475 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
479 /* Run in a single cache-line */
481 mcr p15, 0, r0, c1, c0, 0
487 #ifdef CONFIG_DISABLE_TCM
491 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
497 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
499 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
504 #ifdef CONFIG_PERIPORT_REMAP
505 /* Peri port setup */
506 ldr r0, =CONFIG_PERIPORT_BASE
507 orr r0, r0, #CONFIG_PERIPORT_SIZE
508 mcr p15,0,r0,c15,c2,4
512 * Go setup Memory and board specific bits prior to relocation.
514 bl lowlevel_init /* go setup pll,mux,memory */
516 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
517 relocate: /* relocate U-Boot to RAM */
518 adr r0, _start /* r0 <- current position of code */
519 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
520 cmp r0, r1 /* don't reloc during debug */
523 ldr r2, _armboot_start
525 sub r2, r3, r2 /* r2 <- size of armboot */
526 add r2, r0, r2 /* r2 <- source end address */
529 ldmia r0!, {r3-r10} /* copy from source address [r0] */
530 stmia r1!, {r3-r10} /* copy to target address [r1] */
531 cmp r0, r2 /* until source end address [r2] */
533 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
535 #ifdef CONFIG_ENABLE_MMU
537 /* enable domain access */
539 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
541 /* Set the TTB register */
542 ldr r0, _mmu_table_base
543 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
547 mcr p15, 0, r1, c2, c0, 0
550 mrc p15, 0, r0, c1, c0, 0
551 orr r0, r0, #1 /* Set CR_M to enable MMU */
553 /* Prepare to enable the MMU */
563 /* Run in a single cache-line */
566 mcr p15, 0, r0, c1, c0, 0
573 /* Set up the stack */
575 ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
576 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
577 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
578 sub sp, r0, #12 /* leave 3 words for abort-stack */
579 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
582 ldr r0, _bss_start /* find start of bss segment */
583 ldr r1, _bss_end /* stop here */
584 mov r2, #0 /* clear */
587 str r2, [r0] /* clear loop... */
592 #ifndef CONFIG_NAND_SPL
593 ldr pc, _start_armboot
602 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
604 #ifdef CONFIG_ENABLE_MMU
609 #ifndef CONFIG_NAND_SPL
611 * we assume that cache operation is done before. (eg. cleanup_before_linux())
612 * actually, we don't need to do anything about cache if not use d-cache in
613 * U-Boot. So, in this function we clean only MMU. by scsuh
615 * void theLastJump(void *kernel, int arch_num, uint boot_params);
617 #ifdef CONFIG_ENABLE_MMU
622 ldr r4, _TEXT_PHY_BASE
623 adr r5, phy_last_jump
631 mrc p15, 0, r0, c1, c0, 0
632 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
633 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
634 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
635 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
636 mcr p15, 0, r0, c1, c0, 0
638 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
646 *************************************************************************
650 *************************************************************************
655 #define S_FRAME_SIZE 72
677 #define MODE_SVC 0x13
681 * use bad_save_user_regs for abort/prefetch/undef/swi ...
684 .macro bad_save_user_regs
685 /* carve out a frame on current user stack */
686 sub sp, sp, #S_FRAME_SIZE
687 /* Save user registers (now in svc mode) r0-r12 */
690 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
691 ldr r2, _armboot_start
692 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
693 /* set base 2 words into abort stack */
694 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8)
696 ldr r2, IRQ_STACK_START_IN
698 /* get values for "aborted" pc and cpsr (into parm regs) */
700 /* grab pointer to old stack */
701 add r0, sp, #S_FRAME_SIZE
705 /* save sp_SVC, lr_SVC, pc, cpsr */
707 /* save current stack into r0 (param register) */
712 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
713 /* setup our mode stack (enter in banked mode) */
714 ldr r13, _armboot_start
715 /* move past malloc pool */
716 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
717 /* move to reserved a couple spots for abort stack */
718 sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8)
720 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
723 /* save caller lr in position 0 of saved stack */
727 /* save spsr in position 1 of saved stack */
730 /* prepare SVC-Mode */
733 /* switch modes, make sure moves will execute */
735 /* capture return pc */
737 /* jump to next instruction & switch modes. */
741 .macro get_bad_stack_swi
742 /* space on current stack for scratch reg. */
744 /* save R0's value. */
746 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
747 /* get data regions start */
748 ldr r0, _armboot_start
749 /* move past malloc pool */
750 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
751 /* move past gbl and a couple spots for abort stack */
752 sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8)
754 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
756 /* save caller lr in position 0 of saved stack */
760 /* save spsr in position 1 of saved stack */
764 /* pop stack entry */
772 undefined_instruction:
775 bl do_undefined_instruction
781 bl do_software_interrupt
812 #endif /* CONFIG_NAND_SPL */