3 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
14 void mx31_uart1_hw_init(void)
16 /* setup pins for UART1 */
17 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
18 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
19 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
20 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
23 void mx31_uart2_hw_init(void)
25 /* setup pins for UART2 */
26 mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
27 mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
28 mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
29 mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
34 * Note: putting several spi setups here makes no sense as they may differ
35 * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
37 void mx31_spi2_hw_init(void)
40 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
41 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
42 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
43 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
44 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
45 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
46 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
48 /* start SPI2 clock */
49 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);