arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * Motherboard Express uATX
   5  * V2M-P1
   6  *
   7  * HBI-0190D
   8  *
   9  * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
  10  * Technical Reference Manual)
  11  *
  12  * WARNING! The hardware described in this file is independent from the
  13  * original variant (vexpress-v2m.dtsi), but there is a strong
  14  * correspondence between the two configurations.
  15  *
  16  * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  17  * CHANGES TO vexpress-v2m.dtsi!
  18  */
  19
  20 / {
  21         smb@8000000 {
  22                 motherboard {
  23                         model = "V2M-P1";
  24                         arm,hbi = <0x190>;
  25                         arm,vexpress,site = <0>;
  26                         arm,v2m-memory-map = "rs1";
  27                         compatible = "arm,vexpress,v2m-p1", "simple-bus";
  28                         #address-cells = <2>; /* SMB chipselect number and offset */
  29                         #size-cells = <1>;
  30                         #interrupt-cells = <1>;
  31                         ranges;
  32
  33                         nor_flash: flash@0,00000000 {
  34                                 compatible = "arm,vexpress-flash", "cfi-flash";
  35                                 reg = <0 0x00000000 0x04000000>,
  36                                       <4 0x00000000 0x04000000>;
  37                                 bank-width = <4>;
  38                                 partitions {
  39                                         compatible = "arm,arm-firmware-suite";
  40                                 };
  41                         };
  42
  43                         psram@1,00000000 {
  44                                 compatible = "arm,vexpress-psram", "mtd-ram";
  45                                 reg = <1 0x00000000 0x02000000>;
  46                                 bank-width = <4>;
  47                         };
  48
  49                         ethernet@2,02000000 {
  50                                 compatible = "smsc,lan9118", "smsc,lan9115";
  51                                 reg = <2 0x02000000 0x10000>;
  52                                 interrupts = <15>;
  53                                 phy-mode = "mii";
  54                                 reg-io-width = <4>;
  55                                 smsc,irq-active-high;
  56                                 smsc,irq-push-pull;
  57                                 vdd33a-supply = <&v2m_fixed_3v3>;
  58                                 vddvario-supply = <&v2m_fixed_3v3>;
  59                         };
  60
  61                         usb@2,03000000 {
  62                                 compatible = "nxp,usb-isp1761";
  63                                 reg = <2 0x03000000 0x20000>;
  64                                 interrupts = <16>;
  65                                 port1-otg;
  66                         };
  67
  68                         iofpga@3,00000000 {
  69                                 compatible = "simple-bus";
  70                                 #address-cells = <1>;
  71                                 #size-cells = <1>;
  72                                 ranges = <0 3 0 0x200000>;
  73
  74                                 v2m_sysreg: sysreg@10000 {
  75                                         compatible = "arm,vexpress-sysreg";
  76                                         reg = <0x010000 0x1000>;
  77                                         #address-cells = <1>;
  78                                         #size-cells = <1>;
  79                                         ranges = <0 0x10000 0x1000>;
  80
  81                                         v2m_led_gpios: gpio@8 {
  82                                                 compatible = "arm,vexpress-sysreg,sys_led";
  83                                                 reg = <0x008 4>;
  84                                                 gpio-controller;
  85                                                 #gpio-cells = <2>;
  86                                         };
  87
  88                                         v2m_mmc_gpios: gpio@48 {
  89                                                 compatible = "arm,vexpress-sysreg,sys_mci";
  90                                                 reg = <0x048 4>;
  91                                                 gpio-controller;
  92                                                 #gpio-cells = <2>;
  93                                         };
  94
  95                                         v2m_flash_gpios: gpio@4c {
  96                                                 compatible = "arm,vexpress-sysreg,sys_flash";
  97                                                 reg = <0x04c 4>;
  98                                                 gpio-controller;
  99                                                 #gpio-cells = <2>;
 100                                         };
 101                                 };
 102
 103                                 v2m_sysctl: sysctl@20000 {
 104                                         compatible = "arm,sp810", "arm,primecell";
 105                                         reg = <0x020000 0x1000>;
 106                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
 107                                         clock-names = "refclk", "timclk", "apb_pclk";
 108                                         #clock-cells = <1>;
 109                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 110                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 111                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 112                                 };
 113
 114                                 /* PCI-E I2C bus */
 115                                 v2m_i2c_pcie: i2c@30000 {
 116                                         compatible = "arm,versatile-i2c";
 117                                         reg = <0x030000 0x1000>;
 118
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121
 122                                         pcie-switch@60 {
 123                                                 compatible = "idt,89hpes32h8";
 124                                                 reg = <0x60>;
 125                                         };
 126                                 };
 127
 128                                 aaci@40000 {
 129                                         compatible = "arm,pl041", "arm,primecell";
 130                                         reg = <0x040000 0x1000>;
 131                                         interrupts = <11>;
 132                                         clocks = <&smbclk>;
 133                                         clock-names = "apb_pclk";
 134                                 };
 135
 136                                 mmci@50000 {
 137                                         compatible = "arm,pl180", "arm,primecell";
 138                                         reg = <0x050000 0x1000>;
 139                                         interrupts = <9>, <10>;
 140                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
 141                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
 142                                         max-frequency = <12000000>;
 143                                         vmmc-supply = <&v2m_fixed_3v3>;
 144                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 145                                         clock-names = "mclk", "apb_pclk";
 146                                 };
 147
 148                                 kmi@60000 {
 149                                         compatible = "arm,pl050", "arm,primecell";
 150                                         reg = <0x060000 0x1000>;
 151                                         interrupts = <12>;
 152                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 153                                         clock-names = "KMIREFCLK", "apb_pclk";
 154                                 };
 155
 156                                 kmi@70000 {
 157                                         compatible = "arm,pl050", "arm,primecell";
 158                                         reg = <0x070000 0x1000>;
 159                                         interrupts = <13>;
 160                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 161                                         clock-names = "KMIREFCLK", "apb_pclk";
 162                                 };
 163
 164                                 v2m_serial0: uart@90000 {
 165                                         compatible = "arm,pl011", "arm,primecell";
 166                                         reg = <0x090000 0x1000>;
 167                                         interrupts = <5>;
 168                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 169                                         clock-names = "uartclk", "apb_pclk";
 170                                 };
 171
 172                                 v2m_serial1: uart@a0000 {
 173                                         compatible = "arm,pl011", "arm,primecell";
 174                                         reg = <0x0a0000 0x1000>;
 175                                         interrupts = <6>;
 176                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 177                                         clock-names = "uartclk", "apb_pclk";
 178                                 };
 179
 180                                 v2m_serial2: uart@b0000 {
 181                                         compatible = "arm,pl011", "arm,primecell";
 182                                         reg = <0x0b0000 0x1000>;
 183                                         interrupts = <7>;
 184                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 185                                         clock-names = "uartclk", "apb_pclk";
 186                                 };
 187
 188                                 v2m_serial3: uart@c0000 {
 189                                         compatible = "arm,pl011", "arm,primecell";
 190                                         reg = <0x0c0000 0x1000>;
 191                                         interrupts = <8>;
 192                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 193                                         clock-names = "uartclk", "apb_pclk";
 194                                 };
 195
 196                                 wdt@f0000 {
 197                                         compatible = "arm,sp805", "arm,primecell";
 198                                         reg = <0x0f0000 0x1000>;
 199                                         interrupts = <0>;
 200                                         clocks = <&v2m_refclk32khz>, <&smbclk>;
 201                                         clock-names = "wdogclk", "apb_pclk";
 202                                 };
 203
 204                                 v2m_timer01: timer@110000 {
 205                                         compatible = "arm,sp804", "arm,primecell";
 206                                         reg = <0x110000 0x1000>;
 207                                         interrupts = <2>;
 208                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 209                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 210                                 };
 211
 212                                 v2m_timer23: timer@120000 {
 213                                         compatible = "arm,sp804", "arm,primecell";
 214                                         reg = <0x120000 0x1000>;
 215                                         interrupts = <3>;
 216                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 217                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 218                                 };
 219
 220                                 /* DVI I2C bus */
 221                                 v2m_i2c_dvi: i2c@160000 {
 222                                         compatible = "arm,versatile-i2c";
 223                                         reg = <0x160000 0x1000>;
 224                                         #address-cells = <1>;
 225                                         #size-cells = <0>;
 226
 227                                         dvi-transmitter@39 {
 228                                                 compatible = "sil,sii9022-tpi", "sil,sii9022";
 229                                                 reg = <0x39>;
 230
 231                                                 ports {
 232                                                         #address-cells = <1>;
 233                                                         #size-cells = <0>;
 234
 235                                                         port@0 {
 236                                                                 reg = <0>;
 237                                                                 dvi_bridge_in: endpoint {
 238                                                                         remote-endpoint = <&clcd_pads>;
 239                                                                 };
 240                                                         };
 241                                                 };
 242                                         };
 243
 244                                         dvi-transmitter@60 {
 245                                                 compatible = "sil,sii9022-cpi", "sil,sii9022";
 246                                                 reg = <0x60>;
 247                                         };
 248                                 };
 249
 250                                 rtc@170000 {
 251                                         compatible = "arm,pl031", "arm,primecell";
 252                                         reg = <0x170000 0x1000>;
 253                                         interrupts = <4>;
 254                                         clocks = <&smbclk>;
 255                                         clock-names = "apb_pclk";
 256                                 };
 257
 258                                 compact-flash@1a0000 {
 259                                         compatible = "arm,vexpress-cf", "ata-generic";
 260                                         reg = <0x1a0000 0x100
 261                                                0x1a0100 0xf00>;
 262                                         reg-shift = <2>;
 263                                 };
 264
 265                                 clcd@1f0000 {
 266                                         compatible = "arm,pl111", "arm,primecell";
 267                                         reg = <0x1f0000 0x1000>;
 268                                         interrupt-names = "combined";
 269                                         interrupts = <14>;
 270                                         clocks = <&v2m_oscclk1>, <&smbclk>;
 271                                         clock-names = "clcdclk", "apb_pclk";
 272                                         /* 800x600 16bpp @36MHz works fine */
 273                                         max-memory-bandwidth = <54000000>;
 274                                         memory-region = <&vram>;
 275
 276                                         port {
 277                                                 clcd_pads: endpoint {
 278                                                         remote-endpoint = <&dvi_bridge_in>;
 279                                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 280                                                 };
 281                                         };
 282                                 };
 283                         };
 284
 285                         v2m_fixed_3v3: fixed-regulator-0 {
 286                                 compatible = "regulator-fixed";
 287                                 regulator-name = "3V3";
 288                                 regulator-min-microvolt = <3300000>;
 289                                 regulator-max-microvolt = <3300000>;
 290                                 regulator-always-on;
 291                         };
 292
 293                         v2m_clk24mhz: clk24mhz {
 294                                 compatible = "fixed-clock";
 295                                 #clock-cells = <0>;
 296                                 clock-frequency = <24000000>;
 297                                 clock-output-names = "v2m:clk24mhz";
 298                         };
 299
 300                         v2m_refclk1mhz: refclk1mhz {
 301                                 compatible = "fixed-clock";
 302                                 #clock-cells = <0>;
 303                                 clock-frequency = <1000000>;
 304                                 clock-output-names = "v2m:refclk1mhz";
 305                         };
 306
 307                         v2m_refclk32khz: refclk32khz {
 308                                 compatible = "fixed-clock";
 309                                 #clock-cells = <0>;
 310                                 clock-frequency = <32768>;
 311                                 clock-output-names = "v2m:refclk32khz";
 312                         };
 313
 314                         leds {
 315                                 compatible = "gpio-leds";
 316
 317                                 user1 {
 318                                         label = "v2m:green:user1";
 319                                         gpios = <&v2m_led_gpios 0 0>;
 320                                         linux,default-trigger = "heartbeat";
 321                                 };
 322
 323                                 user2 {
 324                                         label = "v2m:green:user2";
 325                                         gpios = <&v2m_led_gpios 1 0>;
 326                                         linux,default-trigger = "mmc0";
 327                                 };
 328
 329                                 user3 {
 330                                         label = "v2m:green:user3";
 331                                         gpios = <&v2m_led_gpios 2 0>;
 332                                         linux,default-trigger = "cpu0";
 333                                 };
 334
 335                                 user4 {
 336                                         label = "v2m:green:user4";
 337                                         gpios = <&v2m_led_gpios 3 0>;
 338                                         linux,default-trigger = "cpu1";
 339                                 };
 340
 341                                 user5 {
 342                                         label = "v2m:green:user5";
 343                                         gpios = <&v2m_led_gpios 4 0>;
 344                                         linux,default-trigger = "cpu2";
 345                                 };
 346
 347                                 user6 {
 348                                         label = "v2m:green:user6";
 349                                         gpios = <&v2m_led_gpios 5 0>;
 350                                         linux,default-trigger = "cpu3";
 351                                 };
 352
 353                                 user7 {
 354                                         label = "v2m:green:user7";
 355                                         gpios = <&v2m_led_gpios 6 0>;
 356                                         linux,default-trigger = "cpu4";
 357                                 };
 358
 359                                 user8 {
 360                                         label = "v2m:green:user8";
 361                                         gpios = <&v2m_led_gpios 7 0>;
 362                                         linux,default-trigger = "cpu5";
 363                                 };
 364                         };
 365
 366                         mcc {
 367                                 compatible = "arm,vexpress,config-bus";
 368                                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 369
 370                                 oscclk0 {
 371                                         /* MCC static memory clock */
 372                                         compatible = "arm,vexpress-osc";
 373                                         arm,vexpress-sysreg,func = <1 0>;
 374                                         freq-range = <25000000 60000000>;
 375                                         #clock-cells = <0>;
 376                                         clock-output-names = "v2m:oscclk0";
 377                                 };
 378
 379                                 v2m_oscclk1: oscclk1 {
 380                                         /* CLCD clock */
 381                                         compatible = "arm,vexpress-osc";
 382                                         arm,vexpress-sysreg,func = <1 1>;
 383                                         freq-range = <23750000 65000000>;
 384                                         #clock-cells = <0>;
 385                                         clock-output-names = "v2m:oscclk1";
 386                                 };
 387
 388                                 v2m_oscclk2: oscclk2 {
 389                                         /* IO FPGA peripheral clock */
 390                                         compatible = "arm,vexpress-osc";
 391                                         arm,vexpress-sysreg,func = <1 2>;
 392                                         freq-range = <24000000 24000000>;
 393                                         #clock-cells = <0>;
 394                                         clock-output-names = "v2m:oscclk2";
 395                                 };
 396
 397                                 volt-vio {
 398                                         /* Logic level voltage */
 399                                         compatible = "arm,vexpress-volt";
 400                                         arm,vexpress-sysreg,func = <2 0>;
 401                                         regulator-name = "VIO";
 402                                         regulator-always-on;
 403                                         label = "VIO";
 404                                 };
 405
 406                                 temp-mcc {
 407                                         /* MCC internal operating temperature */
 408                                         compatible = "arm,vexpress-temp";
 409                                         arm,vexpress-sysreg,func = <4 0>;
 410                                         label = "MCC";
 411                                 };
 412
 413                                 reset {
 414                                         compatible = "arm,vexpress-reset";
 415                                         arm,vexpress-sysreg,func = <5 0>;
 416                                 };
 417
 418                                 muxfpga {
 419                                         compatible = "arm,vexpress-muxfpga";
 420                                         arm,vexpress-sysreg,func = <7 0>;
 421                                 };
 422
 423                                 shutdown {
 424                                         compatible = "arm,vexpress-shutdown";
 425                                         arm,vexpress-sysreg,func = <8 0>;
 426                                 };
 427
 428                                 reboot {
 429                                         compatible = "arm,vexpress-reboot";
 430                                         arm,vexpress-sysreg,func = <9 0>;
 431                                 };
 432
 433                                 dvimode {
 434                                         compatible = "arm,vexpress-dvimode";
 435                                         arm,vexpress-sysreg,func = <11 0>;
 436                                 };
 437                         };
 438                 };
 439         };
 440 };