arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/clock/stm32fx-clock.h>
  50 #include <dt-bindings/mfd/stm32f4-rcc.h>
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         clocks {
  57                 clk_hse: clk-hse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <0>;
  61                 };
  62
  63                 clk_lse: clk-lse {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 clk_lsi: clk-lsi {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32000>;
  73                 };
  74
  75                 clk_i2s_ckin: i2s-ckin {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <0>;
  79                 };
  80         };
  81
  82         soc {
  83                 romem: nvmem@1fff7800 {
  84                         compatible = "st,stm32f4-otp";
  85                         reg = <0x1fff7800 0x400>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ts_cal1: calib@22c {
  89                                 reg = <0x22c 0x2>;
  90                         };
  91                         ts_cal2: calib@22e {
  92                                 reg = <0x22e 0x2>;
  93                         };
  94                 };
  95
  96                 timer2: timer@40000000 {
  97                         compatible = "st,stm32-timer";
  98                         reg = <0x40000000 0x400>;
  99                         interrupts = <28>;
 100                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
 101                         status = "disabled";
 102                 };
 103
 104                 timers2: timers@40000000 {
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         compatible = "st,stm32-timers";
 108                         reg = <0x40000000 0x400>;
 109                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
 110                         clock-names = "int";
 111                         status = "disabled";
 112
 113                         pwm {
 114                                 compatible = "st,stm32-pwm";
 115                                 status = "disabled";
 116                         };
 117
 118                         timer@1 {
 119                                 compatible = "st,stm32-timer-trigger";
 120                                 reg = <1>;
 121                                 status = "disabled";
 122                         };
 123                 };
 124
 125                 timer3: timer@40000400 {
 126                         compatible = "st,stm32-timer";
 127                         reg = <0x40000400 0x400>;
 128                         interrupts = <29>;
 129                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 130                         status = "disabled";
 131                 };
 132
 133                 timers3: timers@40000400 {
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                         compatible = "st,stm32-timers";
 137                         reg = <0x40000400 0x400>;
 138                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 139                         clock-names = "int";
 140                         status = "disabled";
 141
 142                         pwm {
 143                                 compatible = "st,stm32-pwm";
 144                                 status = "disabled";
 145                         };
 146
 147                         timer@2 {
 148                                 compatible = "st,stm32-timer-trigger";
 149                                 reg = <2>;
 150                                 status = "disabled";
 151                         };
 152                 };
 153
 154                 timer4: timer@40000800 {
 155                         compatible = "st,stm32-timer";
 156                         reg = <0x40000800 0x400>;
 157                         interrupts = <30>;
 158                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 159                         status = "disabled";
 160                 };
 161
 162                 timers4: timers@40000800 {
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         compatible = "st,stm32-timers";
 166                         reg = <0x40000800 0x400>;
 167                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 168                         clock-names = "int";
 169                         status = "disabled";
 170
 171                         pwm {
 172                                 compatible = "st,stm32-pwm";
 173                                 status = "disabled";
 174                         };
 175
 176                         timer@3 {
 177                                 compatible = "st,stm32-timer-trigger";
 178                                 reg = <3>;
 179                                 status = "disabled";
 180                         };
 181                 };
 182
 183                 timer5: timer@40000c00 {
 184                         compatible = "st,stm32-timer";
 185                         reg = <0x40000c00 0x400>;
 186                         interrupts = <50>;
 187                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 188                 };
 189
 190                 timers5: timers@40000c00 {
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                         compatible = "st,stm32-timers";
 194                         reg = <0x40000C00 0x400>;
 195                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 196                         clock-names = "int";
 197                         status = "disabled";
 198
 199                         pwm {
 200                                 compatible = "st,stm32-pwm";
 201                                 status = "disabled";
 202                         };
 203
 204                         timer@4 {
 205                                 compatible = "st,stm32-timer-trigger";
 206                                 reg = <4>;
 207                                 status = "disabled";
 208                         };
 209                 };
 210
 211                 timer6: timer@40001000 {
 212                         compatible = "st,stm32-timer";
 213                         reg = <0x40001000 0x400>;
 214                         interrupts = <54>;
 215                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 216                         status = "disabled";
 217                 };
 218
 219                 timers6: timers@40001000 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         compatible = "st,stm32-timers";
 223                         reg = <0x40001000 0x400>;
 224                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 225                         clock-names = "int";
 226                         status = "disabled";
 227
 228                         timer@5 {
 229                                 compatible = "st,stm32-timer-trigger";
 230                                 reg = <5>;
 231                                 status = "disabled";
 232                         };
 233                 };
 234
 235                 timer7: timer@40001400 {
 236                         compatible = "st,stm32-timer";
 237                         reg = <0x40001400 0x400>;
 238                         interrupts = <55>;
 239                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 240                         status = "disabled";
 241                 };
 242
 243                 timers7: timers@40001400 {
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         compatible = "st,stm32-timers";
 247                         reg = <0x40001400 0x400>;
 248                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 249                         clock-names = "int";
 250                         status = "disabled";
 251
 252                         timer@6 {
 253                                 compatible = "st,stm32-timer-trigger";
 254                                 reg = <6>;
 255                                 status = "disabled";
 256                         };
 257                 };
 258
 259                 timers12: timers@40001800 {
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         compatible = "st,stm32-timers";
 263                         reg = <0x40001800 0x400>;
 264                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 265                         clock-names = "int";
 266                         status = "disabled";
 267
 268                         pwm {
 269                                 compatible = "st,stm32-pwm";
 270                                 status = "disabled";
 271                         };
 272
 273                         timer@11 {
 274                                 compatible = "st,stm32-timer-trigger";
 275                                 reg = <11>;
 276                                 status = "disabled";
 277                         };
 278                 };
 279
 280                 timers13: timers@40001c00 {
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         compatible = "st,stm32-timers";
 284                         reg = <0x40001C00 0x400>;
 285                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 286                         clock-names = "int";
 287                         status = "disabled";
 288
 289                         pwm {
 290                                 compatible = "st,stm32-pwm";
 291                                 status = "disabled";
 292                         };
 293                 };
 294
 295                 timers14: timers@40002000 {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         compatible = "st,stm32-timers";
 299                         reg = <0x40002000 0x400>;
 300                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 301                         clock-names = "int";
 302                         status = "disabled";
 303
 304                         pwm {
 305                                 compatible = "st,stm32-pwm";
 306                                 status = "disabled";
 307                         };
 308                 };
 309
 310                 rtc: rtc@40002800 {
 311                         compatible = "st,stm32-rtc";
 312                         reg = <0x40002800 0x400>;
 313                         clocks = <&rcc 1 CLK_RTC>;
 314                         clock-names = "ck_rtc";
 315                         assigned-clocks = <&rcc 1 CLK_RTC>;
 316                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 317                         interrupt-parent = <&exti>;
 318                         interrupts = <17 1>;
 319                         interrupt-names = "alarm";
 320                         st,syscfg = <&pwrcfg 0x00 0x100>;
 321                         status = "disabled";
 322                 };
 323
 324                 iwdg: watchdog@40003000 {
 325                         compatible = "st,stm32-iwdg";
 326                         reg = <0x40003000 0x400>;
 327                         clocks = <&clk_lsi>;
 328                         clock-names = "lsi";
 329                         status = "disabled";
 330                 };
 331
 332                 spi2: spi@40003800 {
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         compatible = "st,stm32f4-spi";
 336                         reg = <0x40003800 0x400>;
 337                         interrupts = <36>;
 338                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 339                         status = "disabled";
 340                 };
 341
 342                 spi3: spi@40003c00 {
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         compatible = "st,stm32f4-spi";
 346                         reg = <0x40003c00 0x400>;
 347                         interrupts = <51>;
 348                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 349                         status = "disabled";
 350                 };
 351
 352                 usart2: serial@40004400 {
 353                         compatible = "st,stm32-uart";
 354                         reg = <0x40004400 0x400>;
 355                         interrupts = <38>;
 356                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 357                         status = "disabled";
 358                 };
 359
 360                 usart3: serial@40004800 {
 361                         compatible = "st,stm32-uart";
 362                         reg = <0x40004800 0x400>;
 363                         interrupts = <39>;
 364                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 365                         status = "disabled";
 366                         dmas = <&dma1 1 4 0x400 0x0>,
 367                                <&dma1 3 4 0x400 0x0>;
 368                         dma-names = "rx", "tx";
 369                 };
 370
 371                 usart4: serial@40004c00 {
 372                         compatible = "st,stm32-uart";
 373                         reg = <0x40004c00 0x400>;
 374                         interrupts = <52>;
 375                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 376                         status = "disabled";
 377                 };
 378
 379                 usart5: serial@40005000 {
 380                         compatible = "st,stm32-uart";
 381                         reg = <0x40005000 0x400>;
 382                         interrupts = <53>;
 383                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 384                         status = "disabled";
 385                 };
 386
 387                 i2c1: i2c@40005400 {
 388                         compatible = "st,stm32f4-i2c";
 389                         reg = <0x40005400 0x400>;
 390                         interrupts = <31>,
 391                                      <32>;
 392                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 393                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         status = "disabled";
 397                 };
 398
 399                 dac: dac@40007400 {
 400                         compatible = "st,stm32f4-dac-core";
 401                         reg = <0x40007400 0x400>;
 402                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 403                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 404                         clock-names = "pclk";
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         status = "disabled";
 408
 409                         dac1: dac@1 {
 410                                 compatible = "st,stm32-dac";
 411                                 #io-channels-cells = <1>;
 412                                 reg = <1>;
 413                                 status = "disabled";
 414                         };
 415
 416                         dac2: dac@2 {
 417                                 compatible = "st,stm32-dac";
 418                                 #io-channels-cells = <1>;
 419                                 reg = <2>;
 420                                 status = "disabled";
 421                         };
 422                 };
 423
 424                 usart7: serial@40007800 {
 425                         compatible = "st,stm32-uart";
 426                         reg = <0x40007800 0x400>;
 427                         interrupts = <82>;
 428                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 429                         status = "disabled";
 430                 };
 431
 432                 usart8: serial@40007c00 {
 433                         compatible = "st,stm32-uart";
 434                         reg = <0x40007c00 0x400>;
 435                         interrupts = <83>;
 436                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 437                         status = "disabled";
 438                 };
 439
 440                 timers1: timers@40010000 {
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         compatible = "st,stm32-timers";
 444                         reg = <0x40010000 0x400>;
 445                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 446                         clock-names = "int";
 447                         status = "disabled";
 448
 449                         pwm {
 450                                 compatible = "st,stm32-pwm";
 451                                 status = "disabled";
 452                         };
 453
 454                         timer@0 {
 455                                 compatible = "st,stm32-timer-trigger";
 456                                 reg = <0>;
 457                                 status = "disabled";
 458                         };
 459                 };
 460
 461                 timers8: timers@40010400 {
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         compatible = "st,stm32-timers";
 465                         reg = <0x40010400 0x400>;
 466                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 467                         clock-names = "int";
 468                         status = "disabled";
 469
 470                         pwm {
 471                                 compatible = "st,stm32-pwm";
 472                                 status = "disabled";
 473                         };
 474
 475                         timer@7 {
 476                                 compatible = "st,stm32-timer-trigger";
 477                                 reg = <7>;
 478                                 status = "disabled";
 479                         };
 480                 };
 481
 482                 usart1: serial@40011000 {
 483                         compatible = "st,stm32-uart";
 484                         reg = <0x40011000 0x400>;
 485                         interrupts = <37>;
 486                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 487                         status = "disabled";
 488                         dmas = <&dma2 2 4 0x400 0x0>,
 489                                <&dma2 7 4 0x400 0x0>;
 490                         dma-names = "rx", "tx";
 491                 };
 492
 493                 usart6: serial@40011400 {
 494                         compatible = "st,stm32-uart";
 495                         reg = <0x40011400 0x400>;
 496                         interrupts = <71>;
 497                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 498                         status = "disabled";
 499                 };
 500
 501                 adc: adc@40012000 {
 502                         compatible = "st,stm32f4-adc-core";
 503                         reg = <0x40012000 0x400>;
 504                         interrupts = <18>;
 505                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 506                         clock-names = "adc";
 507                         interrupt-controller;
 508                         #interrupt-cells = <1>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         status = "disabled";
 512
 513                         adc1: adc@0 {
 514                                 compatible = "st,stm32f4-adc";
 515                                 #io-channel-cells = <1>;
 516                                 reg = <0x0>;
 517                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 518                                 interrupt-parent = <&adc>;
 519                                 interrupts = <0>;
 520                                 dmas = <&dma2 0 0 0x400 0x0>;
 521                                 dma-names = "rx";
 522                                 status = "disabled";
 523                         };
 524
 525                         adc2: adc@100 {
 526                                 compatible = "st,stm32f4-adc";
 527                                 #io-channel-cells = <1>;
 528                                 reg = <0x100>;
 529                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 530                                 interrupt-parent = <&adc>;
 531                                 interrupts = <1>;
 532                                 dmas = <&dma2 3 1 0x400 0x0>;
 533                                 dma-names = "rx";
 534                                 status = "disabled";
 535                         };
 536
 537                         adc3: adc@200 {
 538                                 compatible = "st,stm32f4-adc";
 539                                 #io-channel-cells = <1>;
 540                                 reg = <0x200>;
 541                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 542                                 interrupt-parent = <&adc>;
 543                                 interrupts = <2>;
 544                                 dmas = <&dma2 1 2 0x400 0x0>;
 545                                 dma-names = "rx";
 546                                 status = "disabled";
 547                         };
 548                 };
 549
 550                 sdio: sdio@40012c00 {
 551                         compatible = "arm,pl180", "arm,primecell";
 552                         arm,primecell-periphid = <0x00880180>;
 553                         reg = <0x40012c00 0x400>;
 554                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 555                         clock-names = "apb_pclk";
 556                         interrupts = <49>;
 557                         max-frequency = <48000000>;
 558                         status = "disabled";
 559                 };
 560
 561                 spi1: spi@40013000 {
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         compatible = "st,stm32f4-spi";
 565                         reg = <0x40013000 0x400>;
 566                         interrupts = <35>;
 567                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 568                         status = "disabled";
 569                 };
 570
 571                 spi4: spi@40013400 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         compatible = "st,stm32f4-spi";
 575                         reg = <0x40013400 0x400>;
 576                         interrupts = <84>;
 577                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 578                         status = "disabled";
 579                 };
 580
 581                 syscfg: system-config@40013800 {
 582                         compatible = "syscon";
 583                         reg = <0x40013800 0x400>;
 584                 };
 585
 586                 exti: interrupt-controller@40013c00 {
 587                         compatible = "st,stm32-exti";
 588                         interrupt-controller;
 589                         #interrupt-cells = <2>;
 590                         reg = <0x40013C00 0x400>;
 591                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 592                 };
 593
 594                 timers9: timers@40014000 {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         compatible = "st,stm32-timers";
 598                         reg = <0x40014000 0x400>;
 599                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 600                         clock-names = "int";
 601                         status = "disabled";
 602
 603                         pwm {
 604                                 compatible = "st,stm32-pwm";
 605                                 status = "disabled";
 606                         };
 607
 608                         timer@8 {
 609                                 compatible = "st,stm32-timer-trigger";
 610                                 reg = <8>;
 611                                 status = "disabled";
 612                         };
 613                 };
 614
 615                 timers10: timers@40014400 {
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         compatible = "st,stm32-timers";
 619                         reg = <0x40014400 0x400>;
 620                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 621                         clock-names = "int";
 622                         status = "disabled";
 623
 624                         pwm {
 625                                 compatible = "st,stm32-pwm";
 626                                 status = "disabled";
 627                         };
 628                 };
 629
 630                 timers11: timers@40014800 {
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         compatible = "st,stm32-timers";
 634                         reg = <0x40014800 0x400>;
 635                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 636                         clock-names = "int";
 637                         status = "disabled";
 638
 639                         pwm {
 640                                 compatible = "st,stm32-pwm";
 641                                 status = "disabled";
 642                         };
 643                 };
 644
 645                 spi5: spi@40015000 {
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648                         compatible = "st,stm32f4-spi";
 649                         reg = <0x40015000 0x400>;
 650                         interrupts = <85>;
 651                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 652                         status = "disabled";
 653                 };
 654
 655                 spi6: spi@40015400 {
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         compatible = "st,stm32f4-spi";
 659                         reg = <0x40015400 0x400>;
 660                         interrupts = <86>;
 661                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 662                         status = "disabled";
 663                 };
 664
 665                 pwrcfg: power-config@40007000 {
 666                         compatible = "syscon";
 667                         reg = <0x40007000 0x400>;
 668                 };
 669
 670                 ltdc: display-controller@40016800 {
 671                         compatible = "st,stm32-ltdc";
 672                         reg = <0x40016800 0x200>;
 673                         interrupts = <88>, <89>;
 674                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 675                         clocks = <&rcc 1 CLK_LCD>;
 676                         clock-names = "lcd";
 677                         status = "disabled";
 678                 };
 679
 680                 crc: crc@40023000 {
 681                         compatible = "st,stm32f4-crc";
 682                         reg = <0x40023000 0x400>;
 683                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 684                         status = "disabled";
 685                 };
 686
 687                 rcc: rcc@40023810 {
 688                         #reset-cells = <1>;
 689                         #clock-cells = <2>;
 690                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 691                         reg = <0x40023800 0x400>;
 692                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 693                         st,syscfg = <&pwrcfg>;
 694                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 695                         assigned-clock-rates = <1000000>;
 696                 };
 697
 698                 dma1: dma-controller@40026000 {
 699                         compatible = "st,stm32-dma";
 700                         reg = <0x40026000 0x400>;
 701                         interrupts = <11>,
 702                                      <12>,
 703                                      <13>,
 704                                      <14>,
 705                                      <15>,
 706                                      <16>,
 707                                      <17>,
 708                                      <47>;
 709                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 710                         #dma-cells = <4>;
 711                 };
 712
 713                 dma2: dma-controller@40026400 {
 714                         compatible = "st,stm32-dma";
 715                         reg = <0x40026400 0x400>;
 716                         interrupts = <56>,
 717                                      <57>,
 718                                      <58>,
 719                                      <59>,
 720                                      <60>,
 721                                      <68>,
 722                                      <69>,
 723                                      <70>;
 724                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 725                         #dma-cells = <4>;
 726                         st,mem2mem;
 727                 };
 728
 729                 mac: ethernet@40028000 {
 730                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 731                         reg = <0x40028000 0x8000>;
 732                         reg-names = "stmmaceth";
 733                         interrupts = <61>;
 734                         interrupt-names = "macirq";
 735                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 736                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 737                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 738                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 739                         st,syscon = <&syscfg 0x4>;
 740                         snps,pbl = <8>;
 741                         snps,mixed-burst;
 742                         status = "disabled";
 743                 };
 744
 745                 usbotg_hs: usb@40040000 {
 746                         compatible = "snps,dwc2";
 747                         reg = <0x40040000 0x40000>;
 748                         interrupts = <77>;
 749                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 750                         clock-names = "otg";
 751                         status = "disabled";
 752                 };
 753
 754                 usbotg_fs: usb@50000000 {
 755                         compatible = "st,stm32f4x9-fsotg";
 756                         reg = <0x50000000 0x40000>;
 757                         interrupts = <67>;
 758                         clocks = <&rcc 0 39>;
 759                         clock-names = "otg";
 760                         status = "disabled";
 761                 };
 762
 763                 dcmi: dcmi@50050000 {
 764                         compatible = "st,stm32-dcmi";
 765                         reg = <0x50050000 0x400>;
 766                         interrupts = <78>;
 767                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 768                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 769                         clock-names = "mclk";
 770                         pinctrl-names = "default";
 771                         pinctrl-0 = <&dcmi_pins>;
 772                         dmas = <&dma2 1 1 0x414 0x3>;
 773                         dma-names = "tx";
 774                         status = "disabled";
 775                 };
 776
 777                 rng: rng@50060800 {
 778                         compatible = "st,stm32-rng";
 779                         reg = <0x50060800 0x400>;
 780                         interrupts = <80>;
 781                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 782
 783                 };
 784         };
 785 };
 786
 787 &systick {
 788         clocks = <&rcc 1 SYSTICK>;
 789         status = "okay";
 790 };