arch/arm/boot/dts/qcom-ipq4019.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         model = "Qualcomm Technologies, Inc. IPQ4019";
  17         compatible = "qcom,ipq4019";
  18         interrupt-parent = <&intc>;
  19
  20         reserved-memory {
  21                 #address-cells = <0x1>;
  22                 #size-cells = <0x1>;
  23                 ranges;
  24
  25                 smem_region: smem@87e00000 {
  26                         reg = <0x87e00000 0x080000>;
  27                         no-map;
  28                 };
  29
  30                 tz@87e80000 {
  31                         reg = <0x87e80000 0x180000>;
  32                         no-map;
  33                 };
  34         };
  35
  36         aliases {
  37                 spi0 = &blsp1_spi1;
  38                 spi1 = &blsp1_spi2;
  39                 i2c0 = &blsp1_i2c3;
  40                 i2c1 = &blsp1_i2c4;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         enable-method = "qcom,kpss-acc-v2";
  50                         next-level-cache = <&L2>;
  51                         qcom,acc = <&acc0>;
  52                         qcom,saw = <&saw0>;
  53                         reg = <0x0>;
  54                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  55                         clock-frequency = <0>;
  56                         clock-latency = <256000>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                 };
  59
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         next-level-cache = <&L2>;
  65                         qcom,acc = <&acc1>;
  66                         qcom,saw = <&saw1>;
  67                         reg = <0x1>;
  68                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  69                         clock-frequency = <0>;
  70                         clock-latency = <256000>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         enable-method = "qcom,kpss-acc-v2";
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc2>;
  80                         qcom,saw = <&saw2>;
  81                         reg = <0x2>;
  82                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  83                         clock-frequency = <0>;
  84                         clock-latency = <256000>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                 };
  87
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         enable-method = "qcom,kpss-acc-v2";
  92                         next-level-cache = <&L2>;
  93                         qcom,acc = <&acc3>;
  94                         qcom,saw = <&saw3>;
  95                         reg = <0x3>;
  96                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  97                         clock-frequency = <0>;
  98                         clock-latency = <256000>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                 };
 101
 102                 L2: l2-cache {
 103                         compatible = "cache";
 104                         cache-level = <2>;
 105                 };
 106         };
 107
 108         cpu0_opp_table: opp_table0 {
 109                 compatible = "operating-points-v2";
 110                 opp-shared;
 111
 112                 opp-48000000 {
 113                         opp-hz = /bits/ 64 <48000000>;
 114                         clock-latency-ns = <256000>;
 115                 };
 116                 opp-200000000 {
 117                         opp-hz = /bits/ 64 <200000000>;
 118                         clock-latency-ns = <256000>;
 119                 };
 120                 opp-500000000 {
 121                         opp-hz = /bits/ 64 <500000000>;
 122                         clock-latency-ns = <256000>;
 123                 };
 124                 opp-716000000 {
 125                         opp-hz = /bits/ 64 <716000000>;
 126                         clock-latency-ns = <256000>;
 127                 };
 128         };
 129
 130         memory {
 131                 device_type = "memory";
 132                 reg = <0x0 0x0>;
 133         };
 134
 135         pmu {
 136                 compatible = "arm,cortex-a7-pmu";
 137                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 138                                          IRQ_TYPE_LEVEL_HIGH)>;
 139         };
 140
 141         clocks {
 142                 sleep_clk: sleep_clk {
 143                         compatible = "fixed-clock";
 144                         clock-frequency = <32768>;
 145                         #clock-cells = <0>;
 146                 };
 147
 148                 xo: xo {
 149                         compatible = "fixed-clock";
 150                         clock-frequency = <48000000>;
 151                         #clock-cells = <0>;
 152                 };
 153         };
 154
 155         firmware {
 156                 scm {
 157                         compatible = "qcom,scm-ipq4019";
 158                 };
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv7-timer";
 163                 interrupts = <1 2 0xf08>,
 164                              <1 3 0xf08>,
 165                              <1 4 0xf08>,
 166                              <1 1 0xf08>;
 167                 clock-frequency = <48000000>;
 168         };
 169
 170         soc {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 ranges;
 174                 compatible = "simple-bus";
 175
 176                 intc: interrupt-controller@b000000 {
 177                         compatible = "qcom,msm-qgic2";
 178                         interrupt-controller;
 179                         #interrupt-cells = <3>;
 180                         reg = <0x0b000000 0x1000>,
 181                         <0x0b002000 0x1000>;
 182                 };
 183
 184                 gcc: clock-controller@1800000 {
 185                         compatible = "qcom,gcc-ipq4019";
 186                         #clock-cells = <1>;
 187                         #reset-cells = <1>;
 188                         reg = <0x1800000 0x60000>;
 189                 };
 190
 191                 rng@22000 {
 192                         compatible = "qcom,prng";
 193                         reg = <0x22000 0x140>;
 194                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 195                         clock-names = "core";
 196                         status = "disabled";
 197                 };
 198
 199                 tlmm: pinctrl@1000000 {
 200                         compatible = "qcom,ipq4019-pinctrl";
 201                         reg = <0x01000000 0x300000>;
 202                         gpio-controller;
 203                         #gpio-cells = <2>;
 204                         interrupt-controller;
 205                         #interrupt-cells = <2>;
 206                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 207                 };
 208
 209                 blsp_dma: dma@7884000 {
 210                         compatible = "qcom,bam-v1.7.0";
 211                         reg = <0x07884000 0x23000>;
 212                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 214                         clock-names = "bam_clk";
 215                         #dma-cells = <1>;
 216                         qcom,ee = <0>;
 217                         status = "disabled";
 218                 };
 219
 220                 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
 221                         compatible = "qcom,spi-qup-v2.2.1";
 222                         reg = <0x78b5000 0x600>;
 223                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 224                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 225                                  <&gcc GCC_BLSP1_AHB_CLK>;
 226                         clock-names = "core", "iface";
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 230                         dma-names = "rx", "tx";
 231                         status = "disabled";
 232                 };
 233
 234                 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
 235                         compatible = "qcom,spi-qup-v2.2.1";
 236                         reg = <0x78b6000 0x600>;
 237                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 239                                 <&gcc GCC_BLSP1_AHB_CLK>;
 240                         clock-names = "core", "iface";
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 244                         dma-names = "rx", "tx";
 245                         status = "disabled";
 246                 };
 247
 248                 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
 249                         compatible = "qcom,i2c-qup-v2.2.1";
 250                         reg = <0x78b7000 0x600>;
 251                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 253                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 254                         clock-names = "iface", "core";
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 258                         dma-names = "rx", "tx";
 259                         status = "disabled";
 260                 };
 261
 262                 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
 263                         compatible = "qcom,i2c-qup-v2.2.1";
 264                         reg = <0x78b8000 0x600>;
 265                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 267                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 268                         clock-names = "iface", "core";
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 272                         dma-names = "rx", "tx";
 273                         status = "disabled";
 274                 };
 275
 276                 cryptobam: dma@8e04000 {
 277                         compatible = "qcom,bam-v1.7.0";
 278                         reg = <0x08e04000 0x20000>;
 279                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 281                         clock-names = "bam_clk";
 282                         #dma-cells = <1>;
 283                         qcom,ee = <1>;
 284                         qcom,controlled-remotely;
 285                         status = "disabled";
 286                 };
 287
 288                 crypto@8e3a000 {
 289                         compatible = "qcom,crypto-v5.1";
 290                         reg = <0x08e3a000 0x6000>;
 291                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 292                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 293                                  <&gcc GCC_CRYPTO_CLK>;
 294                         clock-names = "iface", "bus", "core";
 295                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 296                         dma-names = "rx", "tx";
 297                         status = "disabled";
 298                 };
 299
 300                 acc0: clock-controller@b088000 {
 301                         compatible = "qcom,kpss-acc-v2";
 302                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 303                 };
 304
 305                 acc1: clock-controller@b098000 {
 306                         compatible = "qcom,kpss-acc-v2";
 307                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 308                 };
 309
 310                 acc2: clock-controller@b0a8000 {
 311                         compatible = "qcom,kpss-acc-v2";
 312                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 313                 };
 314
 315                 acc3: clock-controller@b0b8000 {
 316                         compatible = "qcom,kpss-acc-v2";
 317                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 318                 };
 319
 320                 saw0: regulator@b089000 {
 321                         compatible = "qcom,saw2";
 322                         reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
 323                         regulator;
 324                 };
 325
 326                 saw1: regulator@b099000 {
 327                         compatible = "qcom,saw2";
 328                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 329                         regulator;
 330                 };
 331
 332                 saw2: regulator@b0a9000 {
 333                         compatible = "qcom,saw2";
 334                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 335                         regulator;
 336                 };
 337
 338                 saw3: regulator@b0b9000 {
 339                         compatible = "qcom,saw2";
 340                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 341                         regulator;
 342                 };
 343
 344                 blsp1_uart1: serial@78af000 {
 345                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 346                         reg = <0x78af000 0x200>;
 347                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 348                         status = "disabled";
 349                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 350                                 <&gcc GCC_BLSP1_AHB_CLK>;
 351                         clock-names = "core", "iface";
 352                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 353                         dma-names = "rx", "tx";
 354                 };
 355
 356                 blsp1_uart2: serial@78b0000 {
 357                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 358                         reg = <0x78b0000 0x200>;
 359                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 360                         status = "disabled";
 361                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 362                                 <&gcc GCC_BLSP1_AHB_CLK>;
 363                         clock-names = "core", "iface";
 364                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 365                         dma-names = "rx", "tx";
 366                 };
 367
 368                 watchdog@b017000 {
 369                         compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
 370                         reg = <0xb017000 0x40>;
 371                         clocks = <&sleep_clk>;
 372                         timeout-sec = <10>;
 373                         status = "disabled";
 374                 };
 375
 376                 restart@4ab000 {
 377                         compatible = "qcom,pshold";
 378                         reg = <0x4ab000 0x4>;
 379                 };
 380
 381                 pcie0: pci@40000000 {
 382                         compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
 383                         reg =  <0x40000000 0xf1d
 384                                 0x40000f20 0xa8
 385                                 0x80000 0x2000
 386                                 0x40100000 0x1000>;
 387                         reg-names = "dbi", "elbi", "parf", "config";
 388                         device_type = "pci";
 389                         linux,pci-domain = <0>;
 390                         bus-range = <0x00 0xff>;
 391                         num-lanes = <1>;
 392                         #address-cells = <3>;
 393                         #size-cells = <2>;
 394
 395                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
 396                                  <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
 397
 398                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 399                         interrupt-names = "msi";
 400                         #interrupt-cells = <1>;
 401                         interrupt-map-mask = <0 0 0 0x7>;
 402                         interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 403                                         <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 404                                         <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 405                                         <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 406                         clocks = <&gcc GCC_PCIE_AHB_CLK>,
 407                                  <&gcc GCC_PCIE_AXI_M_CLK>,
 408                                  <&gcc GCC_PCIE_AXI_S_CLK>;
 409                         clock-names = "aux",
 410                                       "master_bus",
 411                                       "slave_bus";
 412
 413                         resets = <&gcc PCIE_AXI_M_ARES>,
 414                                  <&gcc PCIE_AXI_S_ARES>,
 415                                  <&gcc PCIE_PIPE_ARES>,
 416                                  <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 417                                  <&gcc PCIE_AXI_S_XPU_ARES>,
 418                                  <&gcc PCIE_PARF_XPU_ARES>,
 419                                  <&gcc PCIE_PHY_ARES>,
 420                                  <&gcc PCIE_AXI_M_STICKY_ARES>,
 421                                  <&gcc PCIE_PIPE_STICKY_ARES>,
 422                                  <&gcc PCIE_PWR_ARES>,
 423                                  <&gcc PCIE_AHB_ARES>,
 424                                  <&gcc PCIE_PHY_AHB_ARES>;
 425                         reset-names = "axi_m",
 426                                       "axi_s",
 427                                       "pipe",
 428                                       "axi_m_vmid",
 429                                       "axi_s_xpu",
 430                                       "parf",
 431                                       "phy",
 432                                       "axi_m_sticky",
 433                                       "pipe_sticky",
 434                                       "pwr",
 435                                       "ahb",
 436                                       "phy_ahb";
 437
 438                         status = "disabled";
 439                 };
 440
 441                 qpic_bam: dma@7984000 {
 442                         compatible = "qcom,bam-v1.7.0";
 443                         reg = <0x7984000 0x1a000>;
 444                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&gcc GCC_QPIC_CLK>;
 446                         clock-names = "bam_clk";
 447                         #dma-cells = <1>;
 448                         qcom,ee = <0>;
 449                         status = "disabled";
 450                 };
 451
 452                 nand: qpic-nand@79b0000 {
 453                         compatible = "qcom,ipq4019-nand";
 454                         reg = <0x79b0000 0x1000>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         clocks = <&gcc GCC_QPIC_CLK>,
 458                                  <&gcc GCC_QPIC_AHB_CLK>;
 459                         clock-names = "core", "aon";
 460
 461                         dmas = <&qpic_bam 0>,
 462                                <&qpic_bam 1>,
 463                                <&qpic_bam 2>;
 464                         dma-names = "tx", "rx", "cmd";
 465                         status = "disabled";
 466
 467                         nand@0 {
 468                                 reg = <0>;
 469
 470                                 nand-ecc-strength = <4>;
 471                                 nand-ecc-step-size = <512>;
 472                                 nand-bus-width = <8>;
 473                         };
 474                 };
 475
 476                 wifi0: wifi@a000000 {
 477                         compatible = "qcom,ipq4019-wifi";
 478                         reg = <0xa000000 0x200000>;
 479                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 480                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 481                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 482                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 483                                  <&gcc WIFI0_CORE_WARM_RESET>,
 484                                  <&gcc WIFI0_CORE_COLD_RESET>;
 485                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 486                                       "wifi_radio_warm", "wifi_radio_cold",
 487                                       "wifi_core_warm", "wifi_core_cold";
 488                         clocks = <&gcc GCC_WCSS2G_CLK>,
 489                                  <&gcc GCC_WCSS2G_REF_CLK>,
 490                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 491                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 492                                       "wifi_wcss_rtc";
 493                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 494                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 495                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 496                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 497                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 498                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 499                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 500                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 501                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 502                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 503                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 504                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 505                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 506                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 507                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 508                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 509                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 510                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 511                                            "msi4",  "msi5",  "msi6",  "msi7",
 512                                            "msi8",  "msi9", "msi10", "msi11",
 513                                           "msi12", "msi13", "msi14", "msi15",
 514                                           "legacy";
 515                         status = "disabled";
 516                 };
 517
 518                 wifi1: wifi@a800000 {
 519                         compatible = "qcom,ipq4019-wifi";
 520                         reg = <0xa800000 0x200000>;
 521                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 522                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 523                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 524                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 525                                  <&gcc WIFI1_CORE_WARM_RESET>,
 526                                  <&gcc WIFI1_CORE_COLD_RESET>;
 527                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 528                                       "wifi_radio_warm", "wifi_radio_cold",
 529                                       "wifi_core_warm", "wifi_core_cold";
 530                         clocks = <&gcc GCC_WCSS5G_CLK>,
 531                                  <&gcc GCC_WCSS5G_REF_CLK>,
 532                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 533                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 534                                       "wifi_wcss_rtc";
 535                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 536                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 537                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 538                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 539                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 540                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 541                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 542                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 543                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 544                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 545                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 546                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 547                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 548                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 549                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 550                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 551                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 552                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 553                                            "msi4",  "msi5",  "msi6",  "msi7",
 554                                            "msi8",  "msi9", "msi10", "msi11",
 555                                           "msi12", "msi13", "msi14", "msi15",
 556                                           "legacy";
 557                         status = "disabled";
 558                 };
 559         };
 560 };